137 lines · c
1/*2 * OMAP Dual-Mode Timers3 *4 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/5 * Tarun Kanti DebBarma <tarun.kanti@ti.com>6 * Thara Gopinath <thara@ti.com>7 *8 * Platform device conversion and hwmod support.9 *10 * Copyright (C) 2005 Nokia Corporation11 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>12 * PWM and clock framwork support by Timo Teras.13 *14 * This program is free software; you can redistribute it and/or modify it15 * under the terms of the GNU General Public License as published by the16 * Free Software Foundation; either version 2 of the License, or (at your17 * option) any later version.18 *19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.27 *28 * You should have received a copy of the GNU General Public License along29 * with this program; if not, write to the Free Software Foundation, Inc.,30 * 675 Mass Ave, Cambridge, MA 02139, USA.31 */32 33#include <linux/delay.h>34#include <linux/io.h>35#include <linux/platform_device.h>36 37#ifndef __CLOCKSOURCE_DMTIMER_H38#define __CLOCKSOURCE_DMTIMER_H39 40/* clock sources */41#define OMAP_TIMER_SRC_SYS_CLK 0x0042#define OMAP_TIMER_SRC_32_KHZ 0x0143#define OMAP_TIMER_SRC_EXT_CLK 0x0244 45/* timer interrupt enable bits */46#define OMAP_TIMER_INT_CAPTURE (1 << 2)47#define OMAP_TIMER_INT_OVERFLOW (1 << 1)48#define OMAP_TIMER_INT_MATCH (1 << 0)49 50/* trigger types */51#define OMAP_TIMER_TRIGGER_NONE 0x0052#define OMAP_TIMER_TRIGGER_OVERFLOW 0x0153#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x0254 55/* timer capabilities used in hwmod database */56#define OMAP_TIMER_SECURE 0x8000000057#define OMAP_TIMER_ALWON 0x4000000058#define OMAP_TIMER_HAS_PWM 0x2000000059#define OMAP_TIMER_NEEDS_RESET 0x1000000060#define OMAP_TIMER_HAS_DSP_IRQ 0x0800000061 62struct omap_dm_timer {63};64 65u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);66 67/*68 * Do not use the defines below, they are not needed. They should be only69 * used by dmtimer.c and sys_timer related code.70 */71 72/*73 * The interrupt registers are different between v1 and v2 ip.74 * These registers are offsets from timer->iobase.75 */76#define OMAP_TIMER_ID_OFFSET 0x0077#define OMAP_TIMER_OCP_CFG_OFFSET 0x1078 79#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x1480#define OMAP_TIMER_V1_STAT_OFFSET 0x1881#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c82 83#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x2484#define OMAP_TIMER_V2_IRQSTATUS 0x2885#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c86#define OMAP_TIMER_V2_IRQENABLE_CLR 0x3087 88/*89 * The functional registers have a different base on v1 and v2 ip.90 * These registers are offsets from timer->func_base. The func_base91 * is samae as io_base for v1 and io_base + 0x14 for v2 ip.92 *93 */94#define OMAP_TIMER_V2_FUNC_OFFSET 0x1495 96#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x2097#define _OMAP_TIMER_CTRL_OFFSET 0x2498#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)99#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)100#define OMAP_TIMER_CTRL_PT (1 << 12)101#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)102#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)103#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)104#define OMAP_TIMER_CTRL_SCPWM (1 << 7)105#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */106#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */107#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */108#define OMAP_TIMER_CTRL_POSTED (1 << 2)109#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */110#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */111#define _OMAP_TIMER_COUNTER_OFFSET 0x28112#define _OMAP_TIMER_LOAD_OFFSET 0x2c113#define _OMAP_TIMER_TRIGGER_OFFSET 0x30114#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34115#define WP_NONE 0 /* no write pending bit */116#define WP_TCLR (1 << 0)117#define WP_TCRR (1 << 1)118#define WP_TLDR (1 << 2)119#define WP_TTGR (1 << 3)120#define WP_TMAR (1 << 4)121#define WP_TPIR (1 << 5)122#define WP_TNIR (1 << 6)123#define WP_TCVR (1 << 7)124#define WP_TOCR (1 << 8)125#define WP_TOWR (1 << 9)126#define _OMAP_TIMER_MATCH_OFFSET 0x38127#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c128#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40129#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */130#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */131#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */132#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */133#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */134#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */135 136#endif /* __CLOCKSOURCE_DMTIMER_H */137