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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Defines for Mobile High-Definition Link (MHL) interface4 *5 * Copyright (C) 2015, Samsung Electronics, Co., Ltd.6 * Andrzej Hajda <a.hajda@samsung.com>7 *8 * Based on MHL driver for Android devices.9 * Copyright (C) 2013-2014 Silicon Image, Inc.10 */11 12#ifndef __MHL_H__13#define __MHL_H__14 15#include <linux/types.h>16 17/* Device Capabilities Registers */18enum {19 MHL_DCAP_DEV_STATE,20 MHL_DCAP_MHL_VERSION,21 MHL_DCAP_CAT,22 MHL_DCAP_ADOPTER_ID_H,23 MHL_DCAP_ADOPTER_ID_L,24 MHL_DCAP_VID_LINK_MODE,25 MHL_DCAP_AUD_LINK_MODE,26 MHL_DCAP_VIDEO_TYPE,27 MHL_DCAP_LOG_DEV_MAP,28 MHL_DCAP_BANDWIDTH,29 MHL_DCAP_FEATURE_FLAG,30 MHL_DCAP_DEVICE_ID_H,31 MHL_DCAP_DEVICE_ID_L,32 MHL_DCAP_SCRATCHPAD_SIZE,33 MHL_DCAP_INT_STAT_SIZE,34 MHL_DCAP_RESERVED,35 MHL_DCAP_SIZE36};37 38#define MHL_DCAP_CAT_SINK 0x0139#define MHL_DCAP_CAT_SOURCE 0x0240#define MHL_DCAP_CAT_POWER 0x1041#define MHL_DCAP_CAT_PLIM(x) ((x) << 5)42 43#define MHL_DCAP_VID_LINK_RGB444 0x0144#define MHL_DCAP_VID_LINK_YCBCR444 0x0245#define MHL_DCAP_VID_LINK_YCBCR422 0x0446#define MHL_DCAP_VID_LINK_PPIXEL 0x0847#define MHL_DCAP_VID_LINK_ISLANDS 0x1048#define MHL_DCAP_VID_LINK_VGA 0x2049#define MHL_DCAP_VID_LINK_16BPP 0x4050 51#define MHL_DCAP_AUD_LINK_2CH 0x0152#define MHL_DCAP_AUD_LINK_8CH 0x0253 54#define MHL_DCAP_VT_GRAPHICS 0x0055#define MHL_DCAP_VT_PHOTO 0x0256#define MHL_DCAP_VT_CINEMA 0x0457#define MHL_DCAP_VT_GAMES 0x0858#define MHL_DCAP_SUPP_VT 0x8059 60#define MHL_DCAP_LD_DISPLAY 0x0161#define MHL_DCAP_LD_VIDEO 0x0262#define MHL_DCAP_LD_AUDIO 0x0463#define MHL_DCAP_LD_MEDIA 0x0864#define MHL_DCAP_LD_TUNER 0x1065#define MHL_DCAP_LD_RECORD 0x2066#define MHL_DCAP_LD_SPEAKER 0x4067#define MHL_DCAP_LD_GUI 0x8068#define MHL_DCAP_LD_ALL 0xFF69 70#define MHL_DCAP_FEATURE_RCP_SUPPORT 0x0171#define MHL_DCAP_FEATURE_RAP_SUPPORT 0x0272#define MHL_DCAP_FEATURE_SP_SUPPORT 0x0473#define MHL_DCAP_FEATURE_UCP_SEND_SUPPOR 0x0874#define MHL_DCAP_FEATURE_UCP_RECV_SUPPORT 0x1075#define MHL_DCAP_FEATURE_RBP_SUPPORT 0x4076 77/* Extended Device Capabilities Registers */78enum {79 MHL_XDC_ECBUS_SPEEDS,80 MHL_XDC_TMDS_SPEEDS,81 MHL_XDC_ECBUS_ROLES,82 MHL_XDC_LOG_DEV_MAPX,83 MHL_XDC_SIZE84};85 86#define MHL_XDC_ECBUS_S_075 0x0187#define MHL_XDC_ECBUS_S_8BIT 0x0288#define MHL_XDC_ECBUS_S_12BIT 0x0489#define MHL_XDC_ECBUS_D_150 0x1090#define MHL_XDC_ECBUS_D_8BIT 0x2091 92#define MHL_XDC_TMDS_000 0x0093#define MHL_XDC_TMDS_150 0x0194#define MHL_XDC_TMDS_300 0x0295#define MHL_XDC_TMDS_600 0x0496 97/* MHL_XDC_ECBUS_ROLES flags */98#define MHL_XDC_DEV_HOST 0x0199#define MHL_XDC_DEV_DEVICE 0x02100#define MHL_XDC_DEV_CHARGER 0x04101#define MHL_XDC_HID_HOST 0x08102#define MHL_XDC_HID_DEVICE 0x10103 104/* MHL_XDC_LOG_DEV_MAPX flags */105#define MHL_XDC_LD_PHONE 0x01106 107/* Device Status Registers */108enum {109 MHL_DST_CONNECTED_RDY,110 MHL_DST_LINK_MODE,111 MHL_DST_VERSION,112 MHL_DST_SIZE113};114 115/* Offset of DEVSTAT registers */116#define MHL_DST_OFFSET 0x30117#define MHL_DST_REG(name) (MHL_DST_OFFSET + MHL_DST_##name)118 119#define MHL_DST_CONN_DCAP_RDY 0x01120#define MHL_DST_CONN_XDEVCAPP_SUPP 0x02121#define MHL_DST_CONN_POW_STAT 0x04122#define MHL_DST_CONN_PLIM_STAT_MASK 0x38123 124#define MHL_DST_LM_CLK_MODE_MASK 0x07125#define MHL_DST_LM_CLK_MODE_PACKED_PIXEL 0x02126#define MHL_DST_LM_CLK_MODE_NORMAL 0x03127#define MHL_DST_LM_PATH_EN_MASK 0x08128#define MHL_DST_LM_PATH_ENABLED 0x08129#define MHL_DST_LM_PATH_DISABLED 0x00130#define MHL_DST_LM_MUTED_MASK 0x10131 132/* Extended Device Status Registers */133enum {134 MHL_XDS_CURR_ECBUS_MODE,135 MHL_XDS_AVLINK_MODE_STATUS,136 MHL_XDS_AVLINK_MODE_CONTROL,137 MHL_XDS_MULTI_SINK_STATUS,138 MHL_XDS_SIZE139};140 141/* Offset of XDEVSTAT registers */142#define MHL_XDS_OFFSET 0x90143#define MHL_XDS_REG(name) (MHL_XDS_OFFSET + MHL_XDS_##name)144 145/* MHL_XDS_REG_CURR_ECBUS_MODE flags */146#define MHL_XDS_SLOT_MODE_8BIT 0x00147#define MHL_XDS_SLOT_MODE_6BIT 0x01148#define MHL_XDS_ECBUS_S 0x04149#define MHL_XDS_ECBUS_D 0x08150 151#define MHL_XDS_LINK_CLOCK_75MHZ 0x00152#define MHL_XDS_LINK_CLOCK_150MHZ 0x10153#define MHL_XDS_LINK_CLOCK_300MHZ 0x20154#define MHL_XDS_LINK_CLOCK_600MHZ 0x30155 156#define MHL_XDS_LINK_STATUS_NO_SIGNAL 0x00157#define MHL_XDS_LINK_STATUS_CRU_LOCKED 0x01158#define MHL_XDS_LINK_STATUS_TMDS_NORMAL 0x02159#define MHL_XDS_LINK_STATUS_TMDS_RESERVED 0x03160 161#define MHL_XDS_LINK_RATE_1_5_GBPS 0x00162#define MHL_XDS_LINK_RATE_3_0_GBPS 0x01163#define MHL_XDS_LINK_RATE_6_0_GBPS 0x02164#define MHL_XDS_ATT_CAPABLE 0x08165 166#define MHL_XDS_SINK_STATUS_1_HPD_LOW 0x00167#define MHL_XDS_SINK_STATUS_1_HPD_HIGH 0x01168#define MHL_XDS_SINK_STATUS_2_HPD_LOW 0x00169#define MHL_XDS_SINK_STATUS_2_HPD_HIGH 0x04170#define MHL_XDS_SINK_STATUS_3_HPD_LOW 0x00171#define MHL_XDS_SINK_STATUS_3_HPD_HIGH 0x10172#define MHL_XDS_SINK_STATUS_4_HPD_LOW 0x00173#define MHL_XDS_SINK_STATUS_4_HPD_HIGH 0x40174 175/* Interrupt Registers */176enum {177 MHL_INT_RCHANGE,178 MHL_INT_DCHANGE,179 MHL_INT_SIZE180};181 182/* Offset of DEVSTAT registers */183#define MHL_INT_OFFSET 0x20184#define MHL_INT_REG(name) (MHL_INT_OFFSET + MHL_INT_##name)185 186#define MHL_INT_RC_DCAP_CHG 0x01187#define MHL_INT_RC_DSCR_CHG 0x02188#define MHL_INT_RC_REQ_WRT 0x04189#define MHL_INT_RC_GRT_WRT 0x08190#define MHL_INT_RC_3D_REQ 0x10191#define MHL_INT_RC_FEAT_REQ 0x20192#define MHL_INT_RC_FEAT_COMPLETE 0x40193 194#define MHL_INT_DC_EDID_CHG 0x02195 196enum {197 MHL_ACK = 0x33, /* Command or Data byte acknowledge */198 MHL_NACK = 0x34, /* Command or Data byte not acknowledge */199 MHL_ABORT = 0x35, /* Transaction abort */200 MHL_WRITE_STAT = 0xe0, /* Write one status register */201 MHL_SET_INT = 0x60, /* Write one interrupt register */202 MHL_READ_DEVCAP_REG = 0x61, /* Read one register */203 MHL_GET_STATE = 0x62, /* Read CBUS revision level from follower */204 MHL_GET_VENDOR_ID = 0x63, /* Read vendor ID value from follower */205 MHL_SET_HPD = 0x64, /* Set Hot Plug Detect in follower */206 MHL_CLR_HPD = 0x65, /* Clear Hot Plug Detect in follower */207 MHL_SET_CAP_ID = 0x66, /* Set Capture ID for downstream device */208 MHL_GET_CAP_ID = 0x67, /* Get Capture ID from downstream device */209 MHL_MSC_MSG = 0x68, /* VS command to send RCP sub-commands */210 MHL_GET_SC1_ERRORCODE = 0x69, /* Get Vendor-Specific error code */211 MHL_GET_DDC_ERRORCODE = 0x6A, /* Get DDC channel command error code */212 MHL_GET_MSC_ERRORCODE = 0x6B, /* Get MSC command error code */213 MHL_WRITE_BURST = 0x6C, /* Write 1-16 bytes to responder's scratchpad */214 MHL_GET_SC3_ERRORCODE = 0x6D, /* Get channel 3 command error code */215 MHL_WRITE_XSTAT = 0x70, /* Write one extended status register */216 MHL_READ_XDEVCAP_REG = 0x71, /* Read one extended devcap register */217 /* let the rest of these float, they are software specific */218 MHL_READ_EDID_BLOCK,219 MHL_SEND_3D_REQ_OR_FEAT_REQ,220 MHL_READ_DEVCAP,221 MHL_READ_XDEVCAP222};223 224/* MSC message types */225enum {226 MHL_MSC_MSG_RCP = 0x10, /* RCP sub-command */227 MHL_MSC_MSG_RCPK = 0x11, /* RCP Acknowledge sub-command */228 MHL_MSC_MSG_RCPE = 0x12, /* RCP Error sub-command */229 MHL_MSC_MSG_RAP = 0x20, /* Mode Change Warning sub-command */230 MHL_MSC_MSG_RAPK = 0x21, /* MCW Acknowledge sub-command */231 MHL_MSC_MSG_RBP = 0x22, /* Remote Button Protocol sub-command */232 MHL_MSC_MSG_RBPK = 0x23, /* RBP Acknowledge sub-command */233 MHL_MSC_MSG_RBPE = 0x24, /* RBP Error sub-command */234 MHL_MSC_MSG_UCP = 0x30, /* UCP sub-command */235 MHL_MSC_MSG_UCPK = 0x31, /* UCP Acknowledge sub-command */236 MHL_MSC_MSG_UCPE = 0x32, /* UCP Error sub-command */237 MHL_MSC_MSG_RUSB = 0x40, /* Request USB host role */238 MHL_MSC_MSG_RUSBK = 0x41, /* Acknowledge request for USB host role */239 MHL_MSC_MSG_RHID = 0x42, /* Request HID host role */240 MHL_MSC_MSG_RHIDK = 0x43, /* Acknowledge request for HID host role */241 MHL_MSC_MSG_ATT = 0x50, /* Request attention sub-command */242 MHL_MSC_MSG_ATTK = 0x51, /* ATT Acknowledge sub-command */243 MHL_MSC_MSG_BIST_TRIGGER = 0x60,244 MHL_MSC_MSG_BIST_REQUEST_STAT = 0x61,245 MHL_MSC_MSG_BIST_READY = 0x62,246 MHL_MSC_MSG_BIST_STOP = 0x63,247};248 249/* RAP action codes */250#define MHL_RAP_POLL 0x00 /* Just do an ack */251#define MHL_RAP_CONTENT_ON 0x10 /* Turn content stream ON */252#define MHL_RAP_CONTENT_OFF 0x11 /* Turn content stream OFF */253#define MHL_RAP_CBUS_MODE_DOWN 0x20254#define MHL_RAP_CBUS_MODE_UP 0x21255 256/* RAPK status codes */257#define MHL_RAPK_NO_ERR 0x00 /* RAP action recognized & supported */258#define MHL_RAPK_UNRECOGNIZED 0x01 /* Unknown RAP action code received */259#define MHL_RAPK_UNSUPPORTED 0x02 /* Rcvd RAP action code not supported */260#define MHL_RAPK_BUSY 0x03 /* Responder too busy to respond */261 262/* Bit masks for RCP messages */263#define MHL_RCP_KEY_RELEASED_MASK 0x80264#define MHL_RCP_KEY_ID_MASK 0x7F265 266/*267 * Error status codes for RCPE messages268 */269/* No error. (Not allowed in RCPE messages) */270#define MHL_RCPE_STATUS_NO_ERROR 0x00271/* Unsupported/unrecognized key code */272#define MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE 0x01273/* Responder busy. Initiator may retry message */274#define MHL_RCPE_STATUS_BUSY 0x02275 276/*277 * Error status codes for RBPE messages278 */279/* No error. (Not allowed in RBPE messages) */280#define MHL_RBPE_STATUS_NO_ERROR 0x00281/* Unsupported/unrecognized button code */282#define MHL_RBPE_STATUS_INEFFECTIVE_BUTTON_CODE 0x01283/* Responder busy. Initiator may retry message */284#define MHL_RBPE_STATUS_BUSY 0x02285 286/*287 * Error status codes for UCPE messages288 */289/* No error. (Not allowed in UCPE messages) */290#define MHL_UCPE_STATUS_NO_ERROR 0x00291/* Unsupported/unrecognized key code */292#define MHL_UCPE_STATUS_INEFFECTIVE_KEY_CODE 0x01293 294enum mhl_burst_id {295 MHL_BURST_ID_3D_VIC = 0x10,296 MHL_BURST_ID_3D_DTD = 0x11,297 MHL_BURST_ID_HEV_VIC = 0x20,298 MHL_BURST_ID_HEV_DTDA = 0x21,299 MHL_BURST_ID_HEV_DTDB = 0x22,300 MHL_BURST_ID_VC_ASSIGN = 0x38,301 MHL_BURST_ID_VC_CONFIRM = 0x39,302 MHL_BURST_ID_AUD_DELAY = 0x40,303 MHL_BURST_ID_ADT_BURSTID = 0x41,304 MHL_BURST_ID_BIST_SETUP = 0x51,305 MHL_BURST_ID_BIST_RETURN_STAT = 0x52,306 MHL_BURST_ID_EMSC_SUPPORT = 0x61,307 MHL_BURST_ID_HID_PAYLOAD = 0x62,308 MHL_BURST_ID_BLK_RCV_BUFFER_INFO = 0x63,309 MHL_BURST_ID_BITS_PER_PIXEL_FMT = 0x64,310};311 312struct mhl_burst_blk_rcv_buffer_info {313 __be16 id;314 __le16 size;315} __packed;316 317struct mhl3_burst_header {318 __be16 id;319 u8 checksum;320 u8 total_entries;321 u8 sequence_index;322} __packed;323 324struct mhl_burst_bits_per_pixel_fmt {325 struct mhl3_burst_header hdr;326 u8 num_entries;327 struct {328 u8 stream_id;329 u8 pixel_format;330 } __packed desc[];331} __packed;332 333struct mhl_burst_emsc_support {334 struct mhl3_burst_header hdr;335 u8 num_entries;336 __be16 burst_id[];337} __packed;338 339struct mhl_burst_audio_descr {340 struct mhl3_burst_header hdr;341 u8 flags;342 u8 short_desc[9];343} __packed;344 345/*346 * MHL3 infoframe related definitions347 */348 349#define MHL3_IEEE_OUI 0x7ca61d350#define MHL3_INFOFRAME_SIZE 15351 352enum mhl3_video_format {353 MHL3_VIDEO_FORMAT_NONE,354 MHL3_VIDEO_FORMAT_3D,355 MHL3_VIDEO_FORMAT_MULTI_VIEW,356 MHL3_VIDEO_FORMAT_DUAL_3D357};358 359enum mhl3_3d_format_type {360 MHL3_3D_FORMAT_TYPE_FS, /* frame sequential */361 MHL3_3D_FORMAT_TYPE_TB, /* top-bottom */362 MHL3_3D_FORMAT_TYPE_LR, /* left-right */363 MHL3_3D_FORMAT_TYPE_FS_TB, /* frame sequential, top-bottom */364 MHL3_3D_FORMAT_TYPE_FS_LR, /* frame sequential, left-right */365 MHL3_3D_FORMAT_TYPE_TB_LR /* top-bottom, left-right */366};367 368struct mhl3_infoframe {369 unsigned char version;370 enum mhl3_video_format video_format;371 enum mhl3_3d_format_type format_type;372 bool sep_audio;373 int hev_format;374 int av_delay;375};376 377#endif /* __MHL_H__ */378