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1/*2 * Copyright © 2008 Keith Packard3 *4 * Permission to use, copy, modify, distribute, and sell this software and its5 * documentation for any purpose is hereby granted without fee, provided that6 * the above copyright notice appear in all copies and that both that copyright7 * notice and this permission notice appear in supporting documentation, and8 * that the name of the copyright holders not be used in advertising or9 * publicity pertaining to distribution of the software without specific,10 * written prior permission. The copyright holders make no representations11 * about the suitability of this software for any purpose. It is provided "as12 * is" without express or implied warranty.13 *14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE20 * OF THIS SOFTWARE.21 */22 23#ifndef _DRM_DP_H_24#define _DRM_DP_H_25 26#include <linux/types.h>27 28/*29 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that30 * DP and DPCD versions are independent. Differences from 1.0 are not noted,31 * 1.0 devices basically don't exist in the wild.32 *33 * Abbreviations, in chronological order:34 *35 * eDP: Embedded DisplayPort version 136 * DPI: DisplayPort Interoperability Guideline v1.1a37 * 1.2: DisplayPort 1.238 * MST: Multistream Transport - part of DP 1.2a39 *40 * 1.2 formally includes both eDP and DPI definitions.41 */42 43/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */44#define DP_MSA_MISC_SYNC_CLOCK (1 << 0)45#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)46#define DP_MSA_MISC_STEREO_NO_3D (0 << 9)47#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)48#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)49/* bits per component for non-RAW */50#define DP_MSA_MISC_6_BPC (0 << 5)51#define DP_MSA_MISC_8_BPC (1 << 5)52#define DP_MSA_MISC_10_BPC (2 << 5)53#define DP_MSA_MISC_12_BPC (3 << 5)54#define DP_MSA_MISC_16_BPC (4 << 5)55/* bits per component for RAW */56#define DP_MSA_MISC_RAW_6_BPC (1 << 5)57#define DP_MSA_MISC_RAW_7_BPC (2 << 5)58#define DP_MSA_MISC_RAW_8_BPC (3 << 5)59#define DP_MSA_MISC_RAW_10_BPC (4 << 5)60#define DP_MSA_MISC_RAW_12_BPC (5 << 5)61#define DP_MSA_MISC_RAW_14_BPC (6 << 5)62#define DP_MSA_MISC_RAW_16_BPC (7 << 5)63/* pixel encoding/colorimetry format */64#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \65 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))66#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)67#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)68#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)69#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)70#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)71#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)72#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)73#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)74#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)75#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)76#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)77#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)78#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)79#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)80#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)81#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)82#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)83#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)84 85#define DP_AUX_MAX_PAYLOAD_BYTES 1686 87#define DP_AUX_I2C_WRITE 0x088#define DP_AUX_I2C_READ 0x189#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x290#define DP_AUX_I2C_MOT 0x491#define DP_AUX_NATIVE_WRITE 0x892#define DP_AUX_NATIVE_READ 0x993 94#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)95#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)96#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)97#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)98 99#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)100#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)101#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)102#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)103 104/* DPCD Field Address Mapping */105 106/* Receiver Capability */107#define DP_DPCD_REV 0x000108# define DP_DPCD_REV_10 0x10109# define DP_DPCD_REV_11 0x11110# define DP_DPCD_REV_12 0x12111# define DP_DPCD_REV_13 0x13112# define DP_DPCD_REV_14 0x14113 114#define DP_MAX_LINK_RATE 0x001115 116#define DP_MAX_LANE_COUNT 0x002117# define DP_MAX_LANE_COUNT_MASK 0x1f118# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */119# define DP_ENHANCED_FRAME_CAP (1 << 7)120 121#define DP_MAX_DOWNSPREAD 0x003122# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)123# define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */124# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)125# define DP_TPS4_SUPPORTED (1 << 7)126 127#define DP_NORP 0x004128 129#define DP_DOWNSTREAMPORT_PRESENT 0x005130# define DP_DWN_STRM_PORT_PRESENT (1 << 0)131# define DP_DWN_STRM_PORT_TYPE_MASK 0x06132# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)133# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)134# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)135# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)136# define DP_FORMAT_CONVERSION (1 << 3)137# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */138 139#define DP_MAIN_LINK_CHANNEL_CODING 0x006140# define DP_CAP_ANSI_8B10B (1 << 0)141# define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */142 143#define DP_DOWN_STREAM_PORT_COUNT 0x007144# define DP_PORT_COUNT_MASK 0x0f145# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */146# define DP_OUI_SUPPORT (1 << 7)147 148#define DP_RECEIVE_PORT_0_CAP_0 0x008149# define DP_LOCAL_EDID_PRESENT (1 << 1)150# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)151# define DP_HBLANK_EXPANSION_CAPABLE (1 << 3)152 153#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009154 155#define DP_RECEIVE_PORT_1_CAP_0 0x00a156#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b157 158#define DP_I2C_SPEED_CAP 0x00c /* DPI */159# define DP_I2C_SPEED_1K 0x01160# define DP_I2C_SPEED_5K 0x02161# define DP_I2C_SPEED_10K 0x04162# define DP_I2C_SPEED_100K 0x08163# define DP_I2C_SPEED_400K 0x10164# define DP_I2C_SPEED_1M 0x20165 166#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */167# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)168# define DP_FRAMING_CHANGE_CAP (1 << 1)169# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */170 171#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */172# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */173# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */174 175#define DP_ADAPTER_CAP 0x00f /* 1.2 */176# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)177# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)178 179#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */180# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */181 182/* Multiple stream transport */183#define DP_FAUX_CAP 0x020 /* 1.2 */184# define DP_FAUX_CAP_1 (1 << 0)185 186#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */187# define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)188# define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)189# define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)190 191#define DP_MSTM_CAP 0x021 /* 1.2 */192# define DP_MST_CAP (1 << 0)193# define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */194 195#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */196 197/* AV_SYNC_DATA_BLOCK 1.2 */198#define DP_AV_GRANULARITY 0x023199# define DP_AG_FACTOR_MASK (0xf << 0)200# define DP_AG_FACTOR_3MS (0 << 0)201# define DP_AG_FACTOR_2MS (1 << 0)202# define DP_AG_FACTOR_1MS (2 << 0)203# define DP_AG_FACTOR_500US (3 << 0)204# define DP_AG_FACTOR_200US (4 << 0)205# define DP_AG_FACTOR_100US (5 << 0)206# define DP_AG_FACTOR_10US (6 << 0)207# define DP_AG_FACTOR_1US (7 << 0)208# define DP_VG_FACTOR_MASK (0xf << 4)209# define DP_VG_FACTOR_3MS (0 << 4)210# define DP_VG_FACTOR_2MS (1 << 4)211# define DP_VG_FACTOR_1MS (2 << 4)212# define DP_VG_FACTOR_500US (3 << 4)213# define DP_VG_FACTOR_200US (4 << 4)214# define DP_VG_FACTOR_100US (5 << 4)215 216#define DP_AUD_DEC_LAT0 0x024217#define DP_AUD_DEC_LAT1 0x025218 219#define DP_AUD_PP_LAT0 0x026220#define DP_AUD_PP_LAT1 0x027221 222#define DP_VID_INTER_LAT 0x028223 224#define DP_VID_PROG_LAT 0x029225 226#define DP_REP_LAT 0x02a227 228#define DP_AUD_DEL_INS0 0x02b229#define DP_AUD_DEL_INS1 0x02c230#define DP_AUD_DEL_INS2 0x02d231/* End of AV_SYNC_DATA_BLOCK */232 233#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */234# define DP_ALPM_CAP (1 << 0)235# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */236# define DP_ALPM_AUX_LESS_CAP (1 << 2) /* eDP 1.5 */237 238#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */239# define DP_AUX_FRAME_SYNC_CAP (1 << 0)240 241#define DP_GUID 0x030 /* 1.2 */242 243#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */244# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)245# define DP_DSC_PASSTHROUGH_IS_SUPPORTED (1 << 1)246# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2)247# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3)248 249#define DP_DSC_REV 0x061250# define DP_DSC_MAJOR_MASK (0xf << 0)251# define DP_DSC_MINOR_MASK (0xf << 4)252# define DP_DSC_MAJOR_SHIFT 0253# define DP_DSC_MINOR_SHIFT 4254 255#define DP_DSC_RC_BUF_BLK_SIZE 0x062256# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0257# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1258# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2259# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3260 261#define DP_DSC_RC_BUF_SIZE 0x063262 263#define DP_DSC_SLICE_CAP_1 0x064264# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)265# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)266# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)267# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)268# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)269# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)270# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)271 272#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065273# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)274# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0275# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1276# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2277# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3278# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4279# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5280# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6281# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7282# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8283 284#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066285# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)286# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1)287 288#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */289 290#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */291# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)292# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK (0x3 << 5) /* eDP 1.5 & DP 2.0 */293# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY (1 << 7) /* eDP 1.5 & DP 2.0 */294 295#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069296# define DP_DSC_RGB (1 << 0)297# define DP_DSC_YCbCr444 (1 << 1)298# define DP_DSC_YCbCr422_Simple (1 << 2)299# define DP_DSC_YCbCr422_Native (1 << 3)300# define DP_DSC_YCbCr420_Native (1 << 4)301 302#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A303# define DP_DSC_8_BPC (1 << 1)304# define DP_DSC_10_BPC (1 << 2)305# define DP_DSC_12_BPC (1 << 3)306 307#define DP_DSC_PEAK_THROUGHPUT 0x06B308# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)309# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0310# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0311# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)312# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)313# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)314# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)315# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)316# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)317# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)318# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)319# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)320# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)321# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)322# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)323# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)324# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)325# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */326# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)327# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4328# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0329# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)330# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)331# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)332# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)333# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)334# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)335# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)336# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)337# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)338# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)339# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)340# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)341# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)342# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)343# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)344 345#define DP_DSC_MAX_SLICE_WIDTH 0x06C346#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560347#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320348 349#define DP_DSC_SLICE_CAP_2 0x06D350# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)351# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)352# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)353 354#define DP_DSC_BITS_PER_PIXEL_INC 0x06F355# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f356# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0357# define DP_DSC_BITS_PER_PIXEL_1_16 0x0358# define DP_DSC_BITS_PER_PIXEL_1_8 0x1359# define DP_DSC_BITS_PER_PIXEL_1_4 0x2360# define DP_DSC_BITS_PER_PIXEL_1_2 0x3361# define DP_DSC_BITS_PER_PIXEL_1_1 0x4362 363#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */364# define DP_PSR_IS_SUPPORTED 1365# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */366# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */367# define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4 /* eDP 1.5, adopted eDP 1.4b SCR */368 369#define DP_PSR_CAPS 0x071 /* XXX 1.2? */370# define DP_PSR_NO_TRAIN_ON_EXIT 1371# define DP_PSR_SETUP_TIME_330 (0 << 1)372# define DP_PSR_SETUP_TIME_275 (1 << 1)373# define DP_PSR_SETUP_TIME_220 (2 << 1)374# define DP_PSR_SETUP_TIME_165 (3 << 1)375# define DP_PSR_SETUP_TIME_110 (4 << 1)376# define DP_PSR_SETUP_TIME_55 (5 << 1)377# define DP_PSR_SETUP_TIME_0 (6 << 1)378# define DP_PSR_SETUP_TIME_MASK (7 << 1)379# define DP_PSR_SETUP_TIME_SHIFT 1380# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */381# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */382# define DP_PSR2_SU_AUX_FRAME_SYNC_NOT_NEEDED (1 << 6)/* eDP 1.5, adopted eDP 1.4b SCR */383 384#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */385#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */386 387/*388 * 0x80-0x8f describe downstream port capabilities, but there are two layouts389 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,390 * each port's descriptor is one byte wide. If it was set, each port's is391 * four bytes wide, starting with the one byte from the base info. As of392 * DP interop v1.1a only VGA defines additional detail.393 */394 395/* offset 0 */396#define DP_DOWNSTREAM_PORT_0 0x80397# define DP_DS_PORT_TYPE_MASK (7 << 0)398# define DP_DS_PORT_TYPE_DP 0399# define DP_DS_PORT_TYPE_VGA 1400# define DP_DS_PORT_TYPE_DVI 2401# define DP_DS_PORT_TYPE_HDMI 3402# define DP_DS_PORT_TYPE_NON_EDID 4403# define DP_DS_PORT_TYPE_DP_DUALMODE 5404# define DP_DS_PORT_TYPE_WIRELESS 6405# define DP_DS_PORT_HPD (1 << 3)406# define DP_DS_NON_EDID_MASK (0xf << 4)407# define DP_DS_NON_EDID_720x480i_60 (1 << 4)408# define DP_DS_NON_EDID_720x480i_50 (2 << 4)409# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)410# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)411# define DP_DS_NON_EDID_1280x720_60 (5 << 4)412# define DP_DS_NON_EDID_1280x720_50 (7 << 4)413/* offset 1 for VGA is maximum megapixels per second / 8 */414/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */415/* offset 2 for VGA/DVI/HDMI */416# define DP_DS_MAX_BPC_MASK (3 << 0)417# define DP_DS_8BPC 0418# define DP_DS_10BPC 1419# define DP_DS_12BPC 2420# define DP_DS_16BPC 3421/* HDMI2.1 PCON FRL CONFIGURATION */422# define DP_PCON_MAX_FRL_BW (7 << 2)423# define DP_PCON_MAX_0GBPS (0 << 2)424# define DP_PCON_MAX_9GBPS (1 << 2)425# define DP_PCON_MAX_18GBPS (2 << 2)426# define DP_PCON_MAX_24GBPS (3 << 2)427# define DP_PCON_MAX_32GBPS (4 << 2)428# define DP_PCON_MAX_40GBPS (5 << 2)429# define DP_PCON_MAX_48GBPS (6 << 2)430# define DP_PCON_SOURCE_CTL_MODE (1 << 5)431 432/* offset 3 for DVI */433# define DP_DS_DVI_DUAL_LINK (1 << 1)434# define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)435/* offset 3 for HDMI */436# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)437# define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)438# define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)439# define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)440# define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)441 442/*443 * VESA DP-to-HDMI PCON Specification adds caps for colorspace444 * conversion in DFP cap DPCD 83h. Sec6.1 Table-3.445 * Based on the available support the source can enable446 * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2447 * DPCD 3052h.448 */449# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5)450# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6)451# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)452 453#define DP_MAX_DOWNSTREAM_PORTS 0x10454 455/* DP Forward error Correction Registers */456#define DP_FEC_CAPABILITY 0x090 /* 1.4 */457# define DP_FEC_CAPABLE (1 << 0)458# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)459# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)460# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)461#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */462 463/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */464#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */465#define DP_PCON_DSC_ENCODER 0x092466# define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)467# define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)468 469/* DP-HDMI2.1 PCON DSC Version */470#define DP_PCON_DSC_VERSION 0x093471# define DP_PCON_DSC_MAJOR_MASK (0xF << 0)472# define DP_PCON_DSC_MINOR_MASK (0xF << 4)473# define DP_PCON_DSC_MAJOR_SHIFT 0474# define DP_PCON_DSC_MINOR_SHIFT 4475 476/* DP-HDMI2.1 PCON DSC RC Buffer block size */477#define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094478# define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)479# define DP_PCON_DSC_RC_BUF_BLK_1KB 0480# define DP_PCON_DSC_RC_BUF_BLK_4KB 1481# define DP_PCON_DSC_RC_BUF_BLK_16KB 2482# define DP_PCON_DSC_RC_BUF_BLK_64KB 3483 484/* DP-HDMI2.1 PCON DSC RC Buffer size */485#define DP_PCON_DSC_RC_BUF_SIZE 0x095486 487/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */488#define DP_PCON_DSC_SLICE_CAP_1 0x096489# define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)490# define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)491# define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)492# define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)493# define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)494# define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)495# define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)496 497#define DP_PCON_DSC_BUF_BIT_DEPTH 0x097498# define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)499# define DP_PCON_DSC_DEPTH_9_BITS 0500# define DP_PCON_DSC_DEPTH_10_BITS 1501# define DP_PCON_DSC_DEPTH_11_BITS 2502# define DP_PCON_DSC_DEPTH_12_BITS 3503# define DP_PCON_DSC_DEPTH_13_BITS 4504# define DP_PCON_DSC_DEPTH_14_BITS 5505# define DP_PCON_DSC_DEPTH_15_BITS 6506# define DP_PCON_DSC_DEPTH_16_BITS 7507# define DP_PCON_DSC_DEPTH_8_BITS 8508 509#define DP_PCON_DSC_BLOCK_PREDICTION 0x098510# define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)511 512#define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099513# define DP_PCON_DSC_ENC_RGB (0x1 << 0)514# define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)515# define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)516# define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)517# define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)518 519#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A520# define DP_PCON_DSC_ENC_8BPC (0x1 << 1)521# define DP_PCON_DSC_ENC_10BPC (0x1 << 2)522# define DP_PCON_DSC_ENC_12BPC (0x1 << 3)523 524#define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B525 526/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */527#define DP_PCON_DSC_SLICE_CAP_2 0x09C528# define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)529# define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)530# define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)531 532/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */533#define DP_PCON_DSC_BPP_INCR 0x09E534# define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)535# define DP_PCON_DSC_ONE_16TH_BPP 0536# define DP_PCON_DSC_ONE_8TH_BPP 1537# define DP_PCON_DSC_ONE_4TH_BPP 2538# define DP_PCON_DSC_ONE_HALF_BPP 3539# define DP_PCON_DSC_ONE_BPP 4540 541/* DP Extended DSC Capabilities */542#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */543#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1544#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2545 546/* DFP Capability Extension */547#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */548 549#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */550# define DP_PANEL_REPLAY_SUPPORT (1 << 0)551# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1)552# define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT (1 << 2) /* eDP 1.5 */553 554#define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1555# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5)556 557#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY 0xb2558#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY 0xb4559 560/* Link Configuration */561#define DP_LINK_BW_SET 0x100562# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */563# define DP_LINK_BW_1_62 0x06564# define DP_LINK_BW_2_7 0x0a565# define DP_LINK_BW_5_4 0x14 /* 1.2 */566# define DP_LINK_BW_8_1 0x1e /* 1.4 */567# define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */568# define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */569# define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */570 571#define DP_LANE_COUNT_SET 0x101572# define DP_LANE_COUNT_MASK 0x0f573# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)574 575#define DP_TRAINING_PATTERN_SET 0x102576# define DP_TRAINING_PATTERN_DISABLE 0577# define DP_TRAINING_PATTERN_1 1578# define DP_TRAINING_PATTERN_2 2579# define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */580# define DP_TRAINING_PATTERN_3 3 /* 1.2 */581# define DP_TRAINING_PATTERN_4 7 /* 1.4 */582# define DP_TRAINING_PATTERN_MASK 0x3583# define DP_TRAINING_PATTERN_MASK_1_4 0xf584 585/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */586# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)587# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)588# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)589# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)590# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)591 592# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)593# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)594 595# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)596# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)597# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)598# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)599 600#define DP_TRAINING_LANE0_SET 0x103601#define DP_TRAINING_LANE1_SET 0x104602#define DP_TRAINING_LANE2_SET 0x105603#define DP_TRAINING_LANE3_SET 0x106604 605# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3606# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0607# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)608# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)609# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)610# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)611# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)612 613# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)614# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)615# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)616# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)617# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)618 619# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3620# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)621 622# define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */623 624#define DP_DOWNSPREAD_CTRL 0x107625# define DP_SPREAD_AMP_0_5 (1 << 4)626# define DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE (1 << 6)627# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */628 629#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108630# define DP_SET_ANSI_8B10B (1 << 0)631# define DP_SET_ANSI_128B132B (1 << 1)632 633#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */634/* bitmask as for DP_I2C_SPEED_CAP */635 636#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */637# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)638# define DP_FRAMING_CHANGE_ENABLE (1 << 1)639# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)640 641#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */642#define DP_LINK_QUAL_LANE1_SET 0x10c643#define DP_LINK_QUAL_LANE2_SET 0x10d644#define DP_LINK_QUAL_LANE3_SET 0x10e645# define DP_LINK_QUAL_PATTERN_DISABLE 0646# define DP_LINK_QUAL_PATTERN_D10_2 1647# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2648# define DP_LINK_QUAL_PATTERN_PRBS7 3649# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4650# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5651# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6652# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7653/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */654# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08655# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10656# define DP_LINK_QUAL_PATTERN_PRSBS9 0x18657# define DP_LINK_QUAL_PATTERN_PRSBS11 0x20658# define DP_LINK_QUAL_PATTERN_PRSBS15 0x28659# define DP_LINK_QUAL_PATTERN_PRSBS23 0x30660# define DP_LINK_QUAL_PATTERN_PRSBS31 0x38661# define DP_LINK_QUAL_PATTERN_CUSTOM 0x40662# define DP_LINK_QUAL_PATTERN_SQUARE 0x48663# define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DISABLED 0x49664# define DP_LINK_QUAL_PATTERN_SQUARE_DEEMPHASIS_DISABLED 0x4a665# define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED 0x4b666 667#define DP_TRAINING_LANE0_1_SET2 0x10f668#define DP_TRAINING_LANE2_3_SET2 0x110669# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)670# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)671# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)672# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)673 674#define DP_MSTM_CTRL 0x111 /* 1.2 */675# define DP_MST_EN (1 << 0)676# define DP_UP_REQ_EN (1 << 1)677# define DP_UPSTREAM_IS_SRC (1 << 2)678 679#define DP_AUDIO_DELAY0 0x112 /* 1.2 */680#define DP_AUDIO_DELAY1 0x113681#define DP_AUDIO_DELAY2 0x114682 683#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */684# define DP_LINK_RATE_SET_SHIFT 0685# define DP_LINK_RATE_SET_MASK (7 << 0)686 687#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */688# define DP_ALPM_ENABLE (1 << 0)689# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) /* eDP 1.5 */690# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */691 692#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */693# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)694# define DP_IRQ_HPD_ENABLE (1 << 1)695 696#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */697# define DP_PWR_NOT_NEEDED (1 << 0)698 699#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */700# define DP_FEC_READY (1 << 0)701# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)702# define DP_FEC_ERR_COUNT_DIS (0 << 1)703# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)704# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)705# define DP_FEC_BIT_ERROR_COUNT (3 << 1)706# define DP_FEC_LANE_SELECT_MASK (3 << 4)707# define DP_FEC_LANE_0_SELECT (0 << 4)708# define DP_FEC_LANE_1_SELECT (1 << 4)709# define DP_FEC_LANE_2_SELECT (2 << 4)710# define DP_FEC_LANE_3_SELECT (3 << 4)711 712#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */713#define DP_SDP_CRC16_128B132B_EN BIT(0)714 715#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */716# define DP_AUX_FRAME_SYNC_VALID (1 << 0)717 718#define DP_DSC_ENABLE 0x160 /* DP 1.4 */719# define DP_DECOMPRESSION_EN (1 << 0)720# define DP_DSC_PASSTHROUGH_EN (1 << 1)721#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */722 723#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */724# define DP_PSR_ENABLE BIT(0)725# define DP_PSR_MAIN_LINK_ACTIVE BIT(1)726# define DP_PSR_CRC_VERIFICATION BIT(2)727# define DP_PSR_FRAME_CAPTURE BIT(3)728# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */729# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */730# define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */731# define DP_PSR_ENABLE_SU_REGION_ET BIT(7) /* eDP 1.5 */732 733#define DP_ADAPTER_CTRL 0x1a0734# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)735 736#define DP_BRANCH_DEVICE_CTRL 0x1a1737# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)738 739#define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */740# define DP_PANEL_REPLAY_ENABLE (1 << 0)741# define DP_PANEL_REPLAY_VSC_SDP_CRC_EN (1 << 1) /* eDP 1.5 */742# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3)743# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4)744# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5)745# define DP_PANEL_REPLAY_SU_ENABLE (1 << 6)746# define DP_PANEL_REPLAY_ENABLE_SU_REGION_ET (1 << 7) /* DP 2.1 */747 748#define PANEL_REPLAY_CONFIG2 0x1b1 /* eDP 1.5 */749# define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED (1 << 0)750# define DP_PANEL_REPLAY_CRC_VERIFICATION (1 << 1)751# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_EN (1 << 2)752# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_SHIFT 3753# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK (0xf << 3)754# define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE (1 << 7)755 756#define DP_PAYLOAD_ALLOCATE_SET 0x1c0757#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1758#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2759 760/* Link/Sink Device Status */761#define DP_SINK_COUNT 0x200762/* prior to 1.2 bit 7 was reserved mbz */763# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))764# define DP_SINK_CP_READY (1 << 6)765 766#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201767# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)768# define DP_AUTOMATED_TEST_REQUEST (1 << 1)769# define DP_CP_IRQ (1 << 2)770# define DP_MCCS_IRQ (1 << 3)771# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */772# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */773# define DP_SINK_SPECIFIC_IRQ (1 << 6)774 775#define DP_LANE0_1_STATUS 0x202776#define DP_LANE2_3_STATUS 0x203777# define DP_LANE_CR_DONE (1 << 0)778# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)779# define DP_LANE_SYMBOL_LOCKED (1 << 2)780 781#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \782 DP_LANE_CHANNEL_EQ_DONE | \783 DP_LANE_SYMBOL_LOCKED)784 785#define DP_LANE_ALIGN_STATUS_UPDATED 0x204786#define DP_INTERLANE_ALIGN_DONE (1 << 0)787#define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */788#define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */789#define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */790#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)791#define DP_LINK_STATUS_UPDATED (1 << 7)792 793#define DP_SINK_STATUS 0x205794# define DP_RECEIVE_PORT_0_STATUS (1 << 0)795# define DP_RECEIVE_PORT_1_STATUS (1 << 1)796# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */797# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */798 799#define DP_ADJUST_REQUEST_LANE0_1 0x206800#define DP_ADJUST_REQUEST_LANE2_3 0x207801# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03802# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0803# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c804# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2805# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30806# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4807# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0808# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6809 810/* DP 2.0 128b/132b Link Layer */811# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)812# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0813# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)814# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4815 816#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c817# define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03818# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0819# define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c820# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2821# define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30822# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4823# define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0824# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6825 826#define DP_TEST_REQUEST 0x218827# define DP_TEST_LINK_TRAINING (1 << 0)828# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)829# define DP_TEST_LINK_EDID_READ (1 << 2)830# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */831# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */832# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */833# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */834 835#define DP_TEST_LINK_RATE 0x219836# define DP_LINK_RATE_162 (0x6)837# define DP_LINK_RATE_27 (0xa)838 839#define DP_TEST_LANE_COUNT 0x220840 841#define DP_TEST_PATTERN 0x221842# define DP_NO_TEST_PATTERN 0x0843# define DP_COLOR_RAMP 0x1844# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2845# define DP_COLOR_SQUARE 0x3846 847#define DP_TEST_H_TOTAL_HI 0x222848#define DP_TEST_H_TOTAL_LO 0x223849 850#define DP_TEST_V_TOTAL_HI 0x224851#define DP_TEST_V_TOTAL_LO 0x225852 853#define DP_TEST_H_START_HI 0x226854#define DP_TEST_H_START_LO 0x227855 856#define DP_TEST_V_START_HI 0x228857#define DP_TEST_V_START_LO 0x229858 859#define DP_TEST_HSYNC_HI 0x22A860# define DP_TEST_HSYNC_POLARITY (1 << 7)861# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)862#define DP_TEST_HSYNC_WIDTH_LO 0x22B863 864#define DP_TEST_VSYNC_HI 0x22C865# define DP_TEST_VSYNC_POLARITY (1 << 7)866# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)867#define DP_TEST_VSYNC_WIDTH_LO 0x22D868 869#define DP_TEST_H_WIDTH_HI 0x22E870#define DP_TEST_H_WIDTH_LO 0x22F871 872#define DP_TEST_V_HEIGHT_HI 0x230873#define DP_TEST_V_HEIGHT_LO 0x231874 875#define DP_TEST_MISC0 0x232876# define DP_TEST_SYNC_CLOCK (1 << 0)877# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)878# define DP_TEST_COLOR_FORMAT_SHIFT 1879# define DP_COLOR_FORMAT_RGB (0 << 1)880# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)881# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)882# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)883# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)884# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)885# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)886# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)887# define DP_TEST_BIT_DEPTH_MASK (7 << 5)888# define DP_TEST_BIT_DEPTH_SHIFT 5889# define DP_TEST_BIT_DEPTH_6 (0 << 5)890# define DP_TEST_BIT_DEPTH_8 (1 << 5)891# define DP_TEST_BIT_DEPTH_10 (2 << 5)892# define DP_TEST_BIT_DEPTH_12 (3 << 5)893# define DP_TEST_BIT_DEPTH_16 (4 << 5)894 895#define DP_TEST_MISC1 0x233896# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)897# define DP_TEST_INTERLACED (1 << 1)898 899#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234900 901#define DP_TEST_MISC0 0x232902 903#define DP_TEST_CRC_R_CR 0x240904#define DP_TEST_CRC_G_Y 0x242905#define DP_TEST_CRC_B_CB 0x244906 907#define DP_TEST_SINK_MISC 0x246908# define DP_TEST_CRC_SUPPORTED (1 << 5)909# define DP_TEST_COUNT_MASK 0xf910 911#define DP_PHY_TEST_PATTERN 0x248912# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7913# define DP_PHY_TEST_PATTERN_NONE 0x0914# define DP_PHY_TEST_PATTERN_D10_2 0x1915# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2916# define DP_PHY_TEST_PATTERN_PRBS7 0x3917# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4918# define DP_PHY_TEST_PATTERN_CP2520 0x5919 920#define DP_PHY_SQUARE_PATTERN 0x249921 922#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A923#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250924#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251925#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252926#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253927#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254928#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255929#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256930#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257931#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258932#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259933 934#define DP_TEST_RESPONSE 0x260935# define DP_TEST_ACK (1 << 0)936# define DP_TEST_NAK (1 << 1)937# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)938 939#define DP_TEST_EDID_CHECKSUM 0x261940 941#define DP_TEST_SINK 0x270942# define DP_TEST_SINK_START (1 << 0)943#define DP_TEST_AUDIO_MODE 0x271944#define DP_TEST_AUDIO_PATTERN_TYPE 0x272945#define DP_TEST_AUDIO_PERIOD_CH1 0x273946#define DP_TEST_AUDIO_PERIOD_CH2 0x274947#define DP_TEST_AUDIO_PERIOD_CH3 0x275948#define DP_TEST_AUDIO_PERIOD_CH4 0x276949#define DP_TEST_AUDIO_PERIOD_CH5 0x277950#define DP_TEST_AUDIO_PERIOD_CH6 0x278951#define DP_TEST_AUDIO_PERIOD_CH7 0x279952#define DP_TEST_AUDIO_PERIOD_CH8 0x27A953 954#define DP_FEC_STATUS 0x280 /* 1.4 */955# define DP_FEC_DECODE_EN_DETECTED (1 << 0)956# define DP_FEC_DECODE_DIS_DETECTED (1 << 1)957 958#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */959 960#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */961# define DP_FEC_ERROR_COUNT_MASK 0x7F962# define DP_FEC_ERR_COUNT_VALID (1 << 7)963 964#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */965# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)966# define DP_PAYLOAD_ACT_HANDLED (1 << 1)967 968#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */969/* up to ID_SLOT_63 at 0x2ff */970 971/* Source Device-specific */972#define DP_SOURCE_OUI 0x300973 974/* Sink Device-specific */975#define DP_SINK_OUI 0x400976 977/* Branch Device-specific */978#define DP_BRANCH_OUI 0x500979#define DP_BRANCH_ID 0x503980#define DP_BRANCH_REVISION_START 0x509981#define DP_BRANCH_HW_REV 0x509982#define DP_BRANCH_SW_REV 0x50A983 984/* Link/Sink Device Power Control */985#define DP_SET_POWER 0x600986# define DP_SET_POWER_D0 0x1987# define DP_SET_POWER_D3 0x2988# define DP_SET_POWER_MASK 0x3989# define DP_SET_POWER_D3_AUX_ON 0x5990 991/* eDP-specific */992#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */993# define DP_EDP_11 0x00994# define DP_EDP_12 0x01995# define DP_EDP_13 0x02996# define DP_EDP_14 0x03997# define DP_EDP_14a 0x04 /* eDP 1.4a */998# define DP_EDP_14b 0x05 /* eDP 1.4b */999 1000#define DP_EDP_GENERAL_CAP_1 0x7011001# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)1002# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)1003# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)1004# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)1005# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)1006# define DP_EDP_FRC_ENABLE_CAP (1 << 5)1007# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)1008# define DP_EDP_SET_POWER_CAP (1 << 7)1009 1010#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x7021011# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)1012# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)1013# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)1014# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)1015# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)1016# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)1017# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)1018# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)1019 1020#define DP_EDP_GENERAL_CAP_2 0x7031021# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)1022# define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4)1023 1024#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */1025# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)1026# define DP_EDP_X_REGION_CAP_SHIFT 01027# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)1028# define DP_EDP_Y_REGION_CAP_SHIFT 41029 1030#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x7201031# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)1032# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)1033# define DP_EDP_FRC_ENABLE (1 << 2)1034# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)1035# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)1036 1037#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x7211038# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)1039# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)1040# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)1041# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)1042# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)1043# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)1044# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)1045# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)1046# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)1047# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */1048# define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1 << 7)1049 1050#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x7221051#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x7231052 1053#define DP_EDP_PWMGEN_BIT_COUNT 0x7241054#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x7251055#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x7261056# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)1057 1058#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x7271059 1060#define DP_EDP_BACKLIGHT_FREQ_SET 0x7281061# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 270001062 1063#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a1064#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b1065#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c1066 1067#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d1068#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e1069#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f1070 1071#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x7321072#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x7331073#define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x7341074 1075#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */1076#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */1077 1078#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */1079# define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)1080# define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 01081# define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3)1082 1083/* Sideband MSG Buffers */1084#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */1085#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */1086#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */1087#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */1088 1089/* DPRX Event Status Indicator */1090#define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */1091#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */1092 1093#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */1094# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)1095# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)1096# define DP_CEC_IRQ (1 << 2)1097 1098#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */1099# define RX_CAP_CHANGED (1 << 0)1100# define LINK_STATUS_CHANGED (1 << 1)1101# define STREAM_STATUS_CHANGED (1 << 2)1102# define HDMI_LINK_STATUS_CHANGED (1 << 3)1103# define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)1104# define DP_TUNNELING_IRQ (1 << 5)1105 1106#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */1107# define DP_PSR_LINK_CRC_ERROR (1 << 0)1108# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)1109# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */1110 1111#define DP_PSR_ESI 0x2007 /* XXX 1.2? */1112# define DP_PSR_CAPS_CHANGE (1 << 0)1113 1114#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */1115# define DP_PSR_SINK_INACTIVE 01116# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 11117# define DP_PSR_SINK_ACTIVE_RFB 21118# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 31119# define DP_PSR_SINK_ACTIVE_RESYNC 41120# define DP_PSR_SINK_INTERNAL_ERROR 71121# define DP_PSR_SINK_STATE_MASK 0x071122 1123#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */1124# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)1125# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 01126# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)1127# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 41128 1129#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */1130# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */1131# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */1132# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */1133# define DP_SU_VALID (1 << 3) /* eDP 1.4 */1134# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */1135# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */1136# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */1137 1138#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */1139# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)1140 1141#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */1142#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */1143#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */1144#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */1145 1146#define DP_PANEL_REPLAY_ERROR_STATUS 0x2020 /* DP 2.1*/1147# define DP_PANEL_REPLAY_LINK_CRC_ERROR (1 << 0)1148# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 1)1149# define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2)1150 1151#define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS 0x2022 /* DP 2.1 */1152# define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0)1153# define DP_SINK_FRAME_LOCKED_SHIFT 31154# define DP_SINK_FRAME_LOCKED_MASK (3 << 3)1155# define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT 51156# define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK (1 << 5)1157 1158/* Extended Receiver Capability: See DP_DPCD_REV for definitions */1159#define DP_DP13_DPCD_REV 0x22001160 1161#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */1162# define DP_GTC_CAP (1 << 0) /* DP 1.3 */1163# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */1164# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */1165# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */1166# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */1167# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */1168# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */1169# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */1170 1171#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */1172# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0)1173# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0)1174# define DP_ADAPTIVE_SYNC_SDP_LENGTH GENMASK(5, 0)1175# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)1176# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4)1177 1178#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */1179# define DP_UHBR10 (1 << 0)1180# define DP_UHBR20 (1 << 1)1181# define DP_UHBR13_5 (1 << 2)1182 1183#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */1184# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)1185# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f1186# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x001187# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x011188# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x021189# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x031190# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x041191# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x051192# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x061193 1194#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x22301195#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x22501196 1197/* DSC Extended Capability Branch Total DSC Resources */1198#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */1199# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)1200# define DP_DSC_DECODER_COUNT_SHIFT 51201#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */1202# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)1203# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)1204# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 11205 1206/* Protocol Converter Extension */1207/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */1208#define DP_CEC_TUNNELING_CAPABILITY 0x30001209# define DP_CEC_TUNNELING_CAPABLE (1 << 0)1210# define DP_CEC_SNOOPING_CAPABLE (1 << 1)1211# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)1212 1213#define DP_CEC_TUNNELING_CONTROL 0x30011214# define DP_CEC_TUNNELING_ENABLE (1 << 0)1215# define DP_CEC_SNOOPING_ENABLE (1 << 1)1216 1217#define DP_CEC_RX_MESSAGE_INFO 0x30021218# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)1219# define DP_CEC_RX_MESSAGE_LEN_SHIFT 01220# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)1221# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)1222# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)1223# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)1224 1225#define DP_CEC_TX_MESSAGE_INFO 0x30031226# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)1227# define DP_CEC_TX_MESSAGE_LEN_SHIFT 01228# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)1229# define DP_CEC_TX_RETRY_COUNT_SHIFT 41230# define DP_CEC_TX_MESSAGE_SEND (1 << 7)1231 1232#define DP_CEC_TUNNELING_IRQ_FLAGS 0x30041233# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)1234# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)1235# define DP_CEC_TX_MESSAGE_SENT (1 << 4)1236# define DP_CEC_TX_LINE_ERROR (1 << 5)1237# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)1238# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)1239 1240#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */1241# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)1242# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)1243# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)1244# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)1245# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)1246# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)1247# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)1248# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)1249#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */1250# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)1251# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)1252# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)1253# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)1254# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)1255# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)1256# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)1257# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)1258 1259#define DP_CEC_RX_MESSAGE_BUFFER 0x30101260#define DP_CEC_TX_MESSAGE_BUFFER 0x30201261#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x101262 1263/* PCON CONFIGURE-1 FRL FOR HDMI SINK */1264#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A1265# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)1266# define DP_PCON_ENABLE_MAX_BW_0GBPS 01267# define DP_PCON_ENABLE_MAX_BW_9GBPS 11268# define DP_PCON_ENABLE_MAX_BW_18GBPS 21269# define DP_PCON_ENABLE_MAX_BW_24GBPS 31270# define DP_PCON_ENABLE_MAX_BW_32GBPS 41271# define DP_PCON_ENABLE_MAX_BW_40GBPS 51272# define DP_PCON_ENABLE_MAX_BW_48GBPS 61273# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)1274# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)1275# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)1276# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)1277# define DP_PCON_ENABLE_HPD_READY (1 << 6)1278# define DP_PCON_ENABLE_HDMI_LINK (1 << 7)1279 1280/* PCON CONFIGURE-2 FRL FOR HDMI SINK */1281#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B1282# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)1283# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)1284# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1)1285# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2)1286# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3)1287# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)1288# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)1289# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)1290# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)1291 1292/* PCON HDMI LINK STATUS */1293#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B1294# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)1295# define DP_PCON_FRL_READY (1 << 1)1296 1297/* PCON HDMI POST FRL STATUS */1298#define DP_PCON_HDMI_POST_FRL_STATUS 0x30361299# define DP_PCON_HDMI_LINK_MODE (1 << 0)1300# define DP_PCON_HDMI_MODE_TMDS 01301# define DP_PCON_HDMI_MODE_FRL 11302# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)1303# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1)1304# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2)1305# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3)1306# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4)1307# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5)1308# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6)1309 1310#define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */1311# define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */1312#define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */1313# define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */1314# define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */1315# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */1316# define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */1317#define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */1318# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */1319# define DP_PCON_ENABLE_DSC_ENCODER (1 << 1)1320# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)1321# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 01322# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 11323# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 21324# define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4)1325# define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4)1326# define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5)1327# define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6)1328 1329/* PCON Downstream HDMI ERROR Status per Lane */1330#define DP_PCON_HDMI_ERROR_STATUS_LN0 0x30371331#define DP_PCON_HDMI_ERROR_STATUS_LN1 0x30381332#define DP_PCON_HDMI_ERROR_STATUS_LN2 0x30391333#define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A1334# define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)1335# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)1336# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1)1337# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)1338 1339/* PCON HDMI CONFIG PPS Override Buffer1340 * Valid Offsets to be added to Base : 0-1271341 */1342#define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x31001343 1344/* PCON HDMI CONFIG PPS Override Parameter: Slice height1345 * Offset-0 8LSBs of the Slice height.1346 * Offset-1 8MSBs of the Slice height.1347 */1348#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x31801349 1350/* PCON HDMI CONFIG PPS Override Parameter: Slice width1351 * Offset-0 8LSBs of the Slice width.1352 * Offset-1 8MSBs of the Slice width.1353 */1354#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x31821355 1356/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel1357 * Offset-0 8LSBs of the bits_per_pixel.1358 * Offset-1 2MSBs of the bits_per_pixel.1359 */1360#define DP_PCON_HDMI_PPS_OVRD_BPP 0x31841361 1362/* HDCP 1.3 and HDCP 2.2 */1363#define DP_AUX_HDCP_BKSV 0x680001364#define DP_AUX_HDCP_RI_PRIME 0x680051365#define DP_AUX_HDCP_AKSV 0x680071366#define DP_AUX_HDCP_AN 0x6800C1367#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)1368#define DP_AUX_HDCP_BCAPS 0x680281369# define DP_BCAPS_REPEATER_PRESENT BIT(1)1370# define DP_BCAPS_HDCP_CAPABLE BIT(0)1371#define DP_AUX_HDCP_BSTATUS 0x680291372# define DP_BSTATUS_REAUTH_REQ BIT(3)1373# define DP_BSTATUS_LINK_FAILURE BIT(2)1374# define DP_BSTATUS_R0_PRIME_READY BIT(1)1375# define DP_BSTATUS_READY BIT(0)1376#define DP_AUX_HDCP_BINFO 0x6802A1377#define DP_AUX_HDCP_KSV_FIFO 0x6802C1378#define DP_AUX_HDCP_AINFO 0x6803B1379 1380/* DP HDCP2.2 parameter offsets in DPCD address space */1381#define DP_HDCP_2_2_REG_RTX_OFFSET 0x690001382#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x690081383#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B1384#define DP_HDCP_2_2_REG_RRX_OFFSET 0x692151385#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D1386#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x692201387#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A01388#define DP_HDCP_2_2_REG_M_OFFSET 0x692B01389#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C01390#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E01391#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F01392#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F81393#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x693181394#define DP_HDCP_2_2_REG_RIV_OFFSET 0x693281395#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x693301396#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x693321397#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x693351398#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x693451399#define DP_HDCP_2_2_REG_V_OFFSET 0x693E01400#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F01401#define DP_HDCP_2_2_REG_K_OFFSET 0x693F31402#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F51403#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x694731404#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x694931405#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x694941406#define DP_HDCP_2_2_REG_DBG_OFFSET 0x695181407 1408/* DP-tunneling */1409#define DP_TUNNELING_OUI 0xe00001410#define DP_TUNNELING_OUI_BYTES 31411 1412#define DP_TUNNELING_DEV_ID 0xe00031413#define DP_TUNNELING_DEV_ID_BYTES 61414 1415#define DP_TUNNELING_HW_REV 0xe00091416#define DP_TUNNELING_HW_REV_MAJOR_SHIFT 41417#define DP_TUNNELING_HW_REV_MAJOR_MASK (0xf << DP_TUNNELING_HW_REV_MAJOR_SHIFT)1418#define DP_TUNNELING_HW_REV_MINOR_SHIFT 01419#define DP_TUNNELING_HW_REV_MINOR_MASK (0xf << DP_TUNNELING_HW_REV_MINOR_SHIFT)1420 1421#define DP_TUNNELING_SW_REV_MAJOR 0xe000a1422#define DP_TUNNELING_SW_REV_MINOR 0xe000b1423 1424#define DP_TUNNELING_CAPABILITIES 0xe000d1425#define DP_IN_BW_ALLOCATION_MODE_SUPPORT (1 << 7)1426#define DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT (1 << 6)1427#define DP_TUNNELING_SUPPORT (1 << 0)1428 1429#define DP_IN_ADAPTER_INFO 0xe000e1430#define DP_IN_ADAPTER_NUMBER_BITS 71431#define DP_IN_ADAPTER_NUMBER_MASK ((1 << DP_IN_ADAPTER_NUMBER_BITS) - 1)1432 1433#define DP_USB4_DRIVER_ID 0xe000f1434#define DP_USB4_DRIVER_ID_BITS 41435#define DP_USB4_DRIVER_ID_MASK ((1 << DP_USB4_DRIVER_ID_BITS) - 1)1436 1437#define DP_USB4_DRIVER_BW_CAPABILITY 0xe00201438#define DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT (1 << 7)1439 1440#define DP_IN_ADAPTER_TUNNEL_INFORMATION 0xe00211441#define DP_GROUP_ID_BITS 31442#define DP_GROUP_ID_MASK ((1 << DP_GROUP_ID_BITS) - 1)1443 1444#define DP_BW_GRANULARITY 0xe00221445#define DP_BW_GRANULARITY_MASK 0x31446 1447#define DP_ESTIMATED_BW 0xe00231448#define DP_ALLOCATED_BW 0xe00241449 1450#define DP_TUNNELING_STATUS 0xe00251451#define DP_BW_ALLOCATION_CAPABILITY_CHANGED (1 << 3)1452#define DP_ESTIMATED_BW_CHANGED (1 << 2)1453#define DP_BW_REQUEST_SUCCEEDED (1 << 1)1454#define DP_BW_REQUEST_FAILED (1 << 0)1455 1456#define DP_TUNNELING_MAX_LINK_RATE 0xe00281457 1458#define DP_TUNNELING_MAX_LANE_COUNT 0xe00291459#define DP_TUNNELING_MAX_LANE_COUNT_MASK 0x1f1460 1461#define DP_DPTX_BW_ALLOCATION_MODE_CONTROL 0xe00301462#define DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE (1 << 7)1463#define DP_UNMASK_BW_ALLOCATION_IRQ (1 << 6)1464 1465#define DP_REQUEST_BW 0xe00311466#define MAX_DP_REQUEST_BW 2551467 1468/* LTTPR: Link Training (LT)-tunable PHY Repeaters */1469#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */1470#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */1471#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */1472#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */1473#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */1474#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */1475#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */1476#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */1477# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)1478/* See DP_128B132B_SUPPORTED_LINK_RATES for values */1479#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */1480#define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */1481 1482enum drm_dp_phy {1483 DP_PHY_DPRX,1484 1485 DP_PHY_LTTPR1,1486 DP_PHY_LTTPR2,1487 DP_PHY_LTTPR3,1488 DP_PHY_LTTPR4,1489 DP_PHY_LTTPR5,1490 DP_PHY_LTTPR6,1491 DP_PHY_LTTPR7,1492 DP_PHY_LTTPR8,1493 1494 DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,1495};1496 1497#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))1498 1499#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */1500#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */1501#define DP_LTTPR_BASE(dp_phy) \1502 (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \1503 ((dp_phy) - DP_PHY_LTTPR1))1504 1505#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \1506 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))1507 1508#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */1509#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \1510 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)1511 1512#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */1513#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \1514 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)1515 1516#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */1517#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */1518#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */1519#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */1520#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \1521 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)1522 1523#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */1524# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)1525# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)1526 1527#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */1528#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \1529 DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)1530/* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */1531 1532#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */1533#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \1534 DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)1535 1536#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */1537 1538#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */1539#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */1540#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */1541#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */1542#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */1543#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */1544#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */1545 1546#define DP_OUI_PHY_REPEATER1 0xf003d /* 1.3 */1547#define DP_OUI_PHY_REPEATER(dp_phy) \1548 DP_LTTPR_REG(dp_phy, DP_OUI_PHY_REPEATER1)1549 1550#define __DP_FEC1_BASE 0xf0290 /* 1.4 */1551#define __DP_FEC2_BASE 0xf0298 /* 1.4 */1552#define DP_FEC_BASE(dp_phy) \1553 (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \1554 ((dp_phy) - DP_PHY_LTTPR1)))1555 1556#define DP_FEC_REG(dp_phy, fec1_reg) \1557 (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)1558 1559#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */1560#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \1561 DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)1562 1563#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */1564#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */1565 1566#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */1567 1568#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */1569 1570/* Repeater modes */1571#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */1572#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */1573 1574/* DP HDCP message start offsets in DPCD address space */1575#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET1576#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET1577#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET1578#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET1579#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET1580#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \1581 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET1582#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET1583#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET1584#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET1585#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET1586#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET1587#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET1588#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET1589 1590#define HDCP_2_2_DP_RXSTATUS_LEN 11591#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))1592#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))1593#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))1594#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))1595#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))1596 1597/* DP 1.2 Sideband message defines */1598/* peer device type - DP 1.2a Table 2-92 */1599#define DP_PEER_DEVICE_NONE 0x01600#define DP_PEER_DEVICE_SOURCE_OR_SST 0x11601#define DP_PEER_DEVICE_MST_BRANCHING 0x21602#define DP_PEER_DEVICE_SST_SINK 0x31603#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x41604 1605/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */1606#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */1607#define DP_LINK_ADDRESS 0x011608#define DP_CONNECTION_STATUS_NOTIFY 0x021609#define DP_ENUM_PATH_RESOURCES 0x101610#define DP_ALLOCATE_PAYLOAD 0x111611#define DP_QUERY_PAYLOAD 0x121612#define DP_RESOURCE_STATUS_NOTIFY 0x131613#define DP_CLEAR_PAYLOAD_ID_TABLE 0x141614#define DP_REMOTE_DPCD_READ 0x201615#define DP_REMOTE_DPCD_WRITE 0x211616#define DP_REMOTE_I2C_READ 0x221617#define DP_REMOTE_I2C_WRITE 0x231618#define DP_POWER_UP_PHY 0x241619#define DP_POWER_DOWN_PHY 0x251620#define DP_SINK_EVENT_NOTIFY 0x301621#define DP_QUERY_STREAM_ENC_STATUS 0x381622#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 01623#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 11624#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 21625 1626/* DP 1.2 MST sideband reply types */1627#define DP_SIDEBAND_REPLY_ACK 0x001628#define DP_SIDEBAND_REPLY_NAK 0x011629 1630/* DP 1.2 MST sideband nak reasons - table 2.84 */1631#define DP_NAK_WRITE_FAILURE 0x011632#define DP_NAK_INVALID_READ 0x021633#define DP_NAK_CRC_FAILURE 0x031634#define DP_NAK_BAD_PARAM 0x041635#define DP_NAK_DEFER 0x051636#define DP_NAK_LINK_FAILURE 0x061637#define DP_NAK_NO_RESOURCES 0x071638#define DP_NAK_DPCD_FAIL 0x081639#define DP_NAK_I2C_NAK 0x091640#define DP_NAK_ALLOCATE_FAIL 0x0a1641 1642#define MODE_I2C_START 11643#define MODE_I2C_WRITE 21644#define MODE_I2C_READ 41645#define MODE_I2C_STOP 81646 1647/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */1648#define DP_MST_PHYSICAL_PORT_0 01649#define DP_MST_LOGICAL_PORT_0 81650 1651#define DP_LINK_CONSTANT_N_VALUE 0x80001652#define DP_LINK_STATUS_SIZE 61653 1654#define DP_BRANCH_OUI_HEADER_SIZE 0xc1655#define DP_RECEIVER_CAP_SIZE 0xf1656#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */1657#define EDP_PSR_RECEIVER_CAP_SIZE 21658#define EDP_DISPLAY_CTL_CAP_SIZE 31659#define DP_LTTPR_COMMON_CAP_SIZE 81660#define DP_LTTPR_PHY_CAP_SIZE 31661 1662#define DP_SDP_AUDIO_TIMESTAMP 0x011663#define DP_SDP_AUDIO_STREAM 0x021664#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */1665#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */1666#define DP_SDP_ISRC 0x06 /* DP 1.2 */1667#define DP_SDP_VSC 0x07 /* DP 1.2 */1668#define DP_SDP_ADAPTIVE_SYNC 0x22 /* DP 1.4 */1669#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */1670#define DP_SDP_PPS 0x10 /* DP 1.4 */1671#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */1672#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */1673 1674/* 0x80+ CEA-861 infoframe types */1675 1676#define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b1677 1678/**1679 * struct dp_sdp_header - DP secondary data packet header1680 * @HB0: Secondary Data Packet ID1681 * @HB1: Secondary Data Packet Type1682 * @HB2: Secondary Data Packet Specific header, Byte 01683 * @HB3: Secondary Data packet Specific header, Byte 11684 */1685struct dp_sdp_header {1686 u8 HB0;1687 u8 HB1;1688 u8 HB2;1689 u8 HB3;1690} __packed;1691 1692#define EDP_SDP_HEADER_REVISION_MASK 0x1F1693#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F1694#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F1695 1696/**1697 * struct dp_sdp - DP secondary data packet1698 * @sdp_header: DP secondary data packet header1699 * @db: DP secondaray data packet data blocks1700 * VSC SDP Payload for PSR1701 * db[0]: Stereo Interface1702 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid1703 * db[2]: CRC value bits 7:0 of the R or Cr component1704 * db[3]: CRC value bits 15:8 of the R or Cr component1705 * db[4]: CRC value bits 7:0 of the G or Y component1706 * db[5]: CRC value bits 15:8 of the G or Y component1707 * db[6]: CRC value bits 7:0 of the B or Cb component1708 * db[7]: CRC value bits 15:8 of the B or Cb component1709 * db[8] - db[31]: Reserved1710 * VSC SDP Payload for Pixel Encoding/Colorimetry Format1711 * db[0] - db[15]: Reserved1712 * db[16]: Pixel Encoding and Colorimetry Formats1713 * db[17]: Dynamic Range and Component Bit Depth1714 * db[18]: Content Type1715 * db[19] - db[31]: Reserved1716 */1717struct dp_sdp {1718 struct dp_sdp_header sdp_header;1719 u8 db[32];1720} __packed;1721 1722#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)1723#define EDP_VSC_PSR_UPDATE_RFB (1<<1)1724#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)1725 1726/**1727 * enum dp_pixelformat - drm DP Pixel encoding formats1728 *1729 * This enum is used to indicate DP VSC SDP Pixel encoding formats.1730 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through1731 * DB18]1732 *1733 * @DP_PIXELFORMAT_RGB: RGB pixel encoding format1734 * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format1735 * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format1736 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format1737 * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format1738 * @DP_PIXELFORMAT_RAW: RAW pixel encoding format1739 * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format1740 */1741enum dp_pixelformat {1742 DP_PIXELFORMAT_RGB = 0,1743 DP_PIXELFORMAT_YUV444 = 0x1,1744 DP_PIXELFORMAT_YUV422 = 0x2,1745 DP_PIXELFORMAT_YUV420 = 0x3,1746 DP_PIXELFORMAT_Y_ONLY = 0x4,1747 DP_PIXELFORMAT_RAW = 0x5,1748 DP_PIXELFORMAT_RESERVED = 0x6,1749};1750 1751/**1752 * enum dp_colorimetry - drm DP Colorimetry formats1753 *1754 * This enum is used to indicate DP VSC SDP Colorimetry formats.1755 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through1756 * DB18] and a name of enum member follows enum drm_colorimetry definition.1757 *1758 * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or1759 * ITU-R BT.601 colorimetry format1760 * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format1761 * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format1762 * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point1763 * (scRGB (IEC 61966-2-2)) colorimetry format1764 * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format1765 * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format1766 * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format1767 * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format1768 * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format1769 * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format1770 * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format1771 * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format1772 * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format1773 * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format1774 */1775enum dp_colorimetry {1776 DP_COLORIMETRY_DEFAULT = 0,1777 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,1778 DP_COLORIMETRY_BT709_YCC = 0x1,1779 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,1780 DP_COLORIMETRY_XVYCC_601 = 0x2,1781 DP_COLORIMETRY_OPRGB = 0x3,1782 DP_COLORIMETRY_XVYCC_709 = 0x3,1783 DP_COLORIMETRY_DCI_P3_RGB = 0x4,1784 DP_COLORIMETRY_SYCC_601 = 0x4,1785 DP_COLORIMETRY_RGB_CUSTOM = 0x5,1786 DP_COLORIMETRY_OPYCC_601 = 0x5,1787 DP_COLORIMETRY_BT2020_RGB = 0x6,1788 DP_COLORIMETRY_BT2020_CYCC = 0x6,1789 DP_COLORIMETRY_BT2020_YCC = 0x7,1790};1791 1792/**1793 * enum dp_dynamic_range - drm DP Dynamic Range1794 *1795 * This enum is used to indicate DP VSC SDP Dynamic Range.1796 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through1797 * DB18]1798 *1799 * @DP_DYNAMIC_RANGE_VESA: VESA range1800 * @DP_DYNAMIC_RANGE_CTA: CTA range1801 */1802enum dp_dynamic_range {1803 DP_DYNAMIC_RANGE_VESA = 0,1804 DP_DYNAMIC_RANGE_CTA = 1,1805};1806 1807/**1808 * enum dp_content_type - drm DP Content Type1809 *1810 * This enum is used to indicate DP VSC SDP Content Types.1811 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through1812 * DB18]1813 * CTA-861-G defines content types and expected processing by a sink device1814 *1815 * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type1816 * @DP_CONTENT_TYPE_GRAPHICS: Graphics type1817 * @DP_CONTENT_TYPE_PHOTO: Photo type1818 * @DP_CONTENT_TYPE_VIDEO: Video type1819 * @DP_CONTENT_TYPE_GAME: Game type1820 */1821enum dp_content_type {1822 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,1823 DP_CONTENT_TYPE_GRAPHICS = 0x01,1824 DP_CONTENT_TYPE_PHOTO = 0x02,1825 DP_CONTENT_TYPE_VIDEO = 0x03,1826 DP_CONTENT_TYPE_GAME = 0x04,1827};1828 1829enum operation_mode {1830 DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,1831 DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,1832 DP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02,1833 DP_AS_SDP_FAVT_TRR_REACHED = 0x031834};1835 1836#endif /* _DRM_DP_H_ */1837