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1/*2 * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sub license,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the12 * next paragraph) shall be included in all copies or substantial portions13 * of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER21 * DEALINGS IN THE SOFTWARE.22 */23 24#ifndef DRM_SCDC_H25#define DRM_SCDC_H26 27#define SCDC_SINK_VERSION 0x0128 29#define SCDC_SOURCE_VERSION 0x0230 31#define SCDC_UPDATE_0 0x1032#define SCDC_READ_REQUEST_TEST (1 << 2)33#define SCDC_CED_UPDATE (1 << 1)34#define SCDC_STATUS_UPDATE (1 << 0)35 36#define SCDC_UPDATE_1 0x1137 38#define SCDC_TMDS_CONFIG 0x2039#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)40#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)41#define SCDC_SCRAMBLING_ENABLE (1 << 0)42 43#define SCDC_SCRAMBLER_STATUS 0x2144#define SCDC_SCRAMBLING_STATUS (1 << 0)45 46#define SCDC_CONFIG_0 0x3047#define SCDC_READ_REQUEST_ENABLE (1 << 0)48 49#define SCDC_STATUS_FLAGS_0 0x4050#define SCDC_CH2_LOCK (1 << 3)51#define SCDC_CH1_LOCK (1 << 2)52#define SCDC_CH0_LOCK (1 << 1)53#define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)54#define SCDC_CLOCK_DETECT (1 << 0)55 56#define SCDC_STATUS_FLAGS_1 0x4157 58#define SCDC_ERR_DET_0_L 0x5059#define SCDC_ERR_DET_0_H 0x5160#define SCDC_ERR_DET_1_L 0x5261#define SCDC_ERR_DET_1_H 0x5362#define SCDC_ERR_DET_2_L 0x5463#define SCDC_ERR_DET_2_H 0x5564#define SCDC_CHANNEL_VALID (1 << 7)65 66#define SCDC_ERR_DET_CHECKSUM 0x5667 68#define SCDC_TEST_CONFIG_0 0xc069#define SCDC_TEST_READ_REQUEST (1 << 7)70#define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)71 72#define SCDC_MANUFACTURER_IEEE_OUI 0xd073#define SCDC_MANUFACTURER_IEEE_OUI_SIZE 374 75#define SCDC_DEVICE_ID 0xd376#define SCDC_DEVICE_ID_SIZE 877 78#define SCDC_DEVICE_HARDWARE_REVISION 0xdb79#define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)80#define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)81 82#define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc83#define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd84 85#define SCDC_MANUFACTURER_SPECIFIC 0xde86#define SCDC_MANUFACTURER_SPECIFIC_SIZE 3487 88#endif89