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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Device Tree binding constants for Actions Semi S500 Clock Management Unit4 *5 * Copyright (c) 2014 Actions Semi Inc.6 * Copyright (c) 2018 LSI-TEC - Caninos Loucos7 */8 9#ifndef __DT_BINDINGS_CLOCK_S500_CMU_H10#define __DT_BINDINGS_CLOCK_S500_CMU_H11 12#define CLK_NONE 013 14/* fixed rate clocks */15#define CLK_LOSC 116#define CLK_HOSC 217 18/* pll clocks */19#define CLK_CORE_PLL 320#define CLK_DEV_PLL 421#define CLK_DDR_PLL 522#define CLK_NAND_PLL 623#define CLK_DISPLAY_PLL 724#define CLK_ETHERNET_PLL 825#define CLK_AUDIO_PLL 926 27/* system clock */28#define CLK_DEV 1029#define CLK_H 1130#define CLK_AHBPREDIV 1231#define CLK_AHB 1332#define CLK_DE 1433#define CLK_BISP 1534#define CLK_VCE 1635#define CLK_VDE 1736 37/* peripheral device clock */38#define CLK_TIMER 1839#define CLK_I2C0 1940#define CLK_I2C1 2041#define CLK_I2C2 2142#define CLK_I2C3 2243#define CLK_PWM0 2344#define CLK_PWM1 2445#define CLK_PWM2 2546#define CLK_PWM3 2647#define CLK_PWM4 2748#define CLK_PWM5 2849#define CLK_SD0 2950#define CLK_SD1 3051#define CLK_SD2 3152#define CLK_SENSOR0 3253#define CLK_SENSOR1 3354#define CLK_SPI0 3455#define CLK_SPI1 3556#define CLK_SPI2 3657#define CLK_SPI3 3758#define CLK_UART0 3859#define CLK_UART1 3960#define CLK_UART2 4061#define CLK_UART3 4162#define CLK_UART4 4263#define CLK_UART5 4364#define CLK_UART6 4465#define CLK_DE1 4566#define CLK_DE2 4667#define CLK_I2SRX 4768#define CLK_I2STX 4869#define CLK_HDMI_AUDIO 4970#define CLK_HDMI 5071#define CLK_SPDIF 5172#define CLK_NAND 5273#define CLK_ECC 5374#define CLK_RMII_REF 5475#define CLK_GPIO 5576 77/* additional clocks */78#define CLK_APB 5679#define CLK_DMAC 5780#define CLK_NIC 5881#define CLK_ETHERNET 5982 83#define CLK_NR_CLKS (CLK_ETHERNET + 1)84 85#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */86