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1// SPDX-License-Identifier: GPL-2.0+2//3// Device Tree binding constants for Actions Semi S900 Clock Management Unit4//5// Copyright (c) 2014 Actions Semi Inc.6// Copyright (c) 2018 Linaro Ltd.7 8#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H9#define __DT_BINDINGS_CLOCK_S900_CMU_H10 11#define CLK_NONE 012 13/* fixed rate clocks */14#define CLK_LOSC 115#define CLK_HOSC 216 17/* pll clocks */18#define CLK_CORE_PLL 319#define CLK_DEV_PLL 420#define CLK_DDR_PLL 521#define CLK_NAND_PLL 622#define CLK_DISPLAY_PLL 723#define CLK_DSI_PLL 824#define CLK_ASSIST_PLL 925#define CLK_AUDIO_PLL 1026 27/* system clock */28#define CLK_CPU 1529#define CLK_DEV 1630#define CLK_NOC 1731#define CLK_NOC_MUX 1832#define CLK_NOC_DIV 1933#define CLK_AHB 2034#define CLK_APB 2135#define CLK_DMAC 2236 37/* peripheral device clock */38#define CLK_GPIO 2339 40#define CLK_BISP 2441#define CLK_CSI0 2542#define CLK_CSI1 2643 44#define CLK_DE0 2745#define CLK_DE1 2846#define CLK_DE2 2947#define CLK_DE3 3048#define CLK_DSI 3249 50#define CLK_GPU 3351#define CLK_GPU_CORE 3452#define CLK_GPU_MEM 3553#define CLK_GPU_SYS 3654 55#define CLK_HDE 3756#define CLK_I2C0 3857#define CLK_I2C1 3958#define CLK_I2C2 4059#define CLK_I2C3 4160#define CLK_I2C4 4261#define CLK_I2C5 4362#define CLK_I2SRX 4463#define CLK_I2STX 4564#define CLK_IMX 4665#define CLK_LCD 4766#define CLK_NAND0 4867#define CLK_NAND1 4968#define CLK_PWM0 5069#define CLK_PWM1 5170#define CLK_PWM2 5271#define CLK_PWM3 5372#define CLK_PWM4 5473#define CLK_PWM5 5574#define CLK_SD0 5675#define CLK_SD1 5776#define CLK_SD2 5877#define CLK_SD3 5978#define CLK_SENSOR 6079#define CLK_SPEED_SENSOR 6180#define CLK_SPI0 6281#define CLK_SPI1 6382#define CLK_SPI2 6483#define CLK_SPI3 6584#define CLK_THERMAL_SENSOR 6685#define CLK_UART0 6786#define CLK_UART1 6887#define CLK_UART2 6988#define CLK_UART3 7089#define CLK_UART4 7190#define CLK_UART5 7291#define CLK_UART6 7392#define CLK_VCE 7493#define CLK_VDE 7594 95#define CLK_USB3_480MPLL0 7696#define CLK_USB3_480MPHY0 7797#define CLK_USB3_5GPHY 7898#define CLK_USB3_CCE 7999#define CLK_USB3_MAC 80100 101#define CLK_TIMER 83102 103#define CLK_HDMI_AUDIO 84104 105#define CLK_24M 85106 107#define CLK_EDP 86108 109#define CLK_24M_EDP 87110#define CLK_EDP_PLL 88111#define CLK_EDP_LINK 89112 113#define CLK_USB2H0_PLLEN 90114#define CLK_USB2H0_PHY 91115#define CLK_USB2H0_CCE 92116#define CLK_USB2H1_PLLEN 93117#define CLK_USB2H1_PHY 94118#define CLK_USB2H1_CCE 95119 120#define CLK_DDR0 96121#define CLK_DDR1 97122#define CLK_DMM 98123 124#define CLK_ETH_MAC 99125#define CLK_RMII_REF 100126 127#define CLK_NR_CLKS (CLK_RMII_REF + 1)128 129#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */130