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1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */2/*3 * Copyright (c) 2023 Amlogic, Inc. All rights reserved.4 * Author: Chuan Liu <chuan.liu@amlogic.com>5 */6 7#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H8#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H9 10#define CLKID_RTC_XTAL_CLKIN			011#define CLKID_RTC_32K_DIV			112#define CLKID_RTC_32K_MUX			213#define CLKID_RTC_32K				314#define CLKID_RTC_CLK				415#define CLKID_SYS_RESET_CTRL			516#define CLKID_SYS_PWR_CTRL			617#define CLKID_SYS_PAD_CTRL			718#define CLKID_SYS_CTRL				819#define CLKID_SYS_TS_PLL			920#define CLKID_SYS_DEV_ARB			1021#define CLKID_SYS_MMC_PCLK			1122#define CLKID_SYS_CPU_CTRL			1223#define CLKID_SYS_JTAG_CTRL			1324#define CLKID_SYS_IR_CTRL			1425#define CLKID_SYS_IRQ_CTRL			1526#define CLKID_SYS_MSR_CLK			1627#define CLKID_SYS_ROM				1728#define CLKID_SYS_UART_F			1829#define CLKID_SYS_CPU_ARB			1930#define CLKID_SYS_RSA				2031#define CLKID_SYS_SAR_ADC			2132#define CLKID_SYS_STARTUP			2233#define CLKID_SYS_SECURE			2334#define CLKID_SYS_SPIFC				2435#define CLKID_SYS_NNA				2536#define CLKID_SYS_ETH_MAC			2637#define CLKID_SYS_GIC				2738#define CLKID_SYS_RAMA				2839#define CLKID_SYS_BIG_NIC			2940#define CLKID_SYS_RAMB				3041#define CLKID_SYS_AUDIO_PCLK			3142#define CLKID_SYS_PWM_KL			3243#define CLKID_SYS_PWM_IJ			3344#define CLKID_SYS_USB				3445#define CLKID_SYS_SD_EMMC_A			3546#define CLKID_SYS_SD_EMMC_C			3647#define CLKID_SYS_PWM_AB			3748#define CLKID_SYS_PWM_CD			3849#define CLKID_SYS_PWM_EF			3950#define CLKID_SYS_PWM_GH			4051#define CLKID_SYS_SPICC_1			4152#define CLKID_SYS_SPICC_0			4253#define CLKID_SYS_UART_A			4354#define CLKID_SYS_UART_B			4455#define CLKID_SYS_UART_C			4556#define CLKID_SYS_UART_D			4657#define CLKID_SYS_UART_E			4758#define CLKID_SYS_I2C_M_A			4859#define CLKID_SYS_I2C_M_B			4960#define CLKID_SYS_I2C_M_C			5061#define CLKID_SYS_I2C_M_D			5162#define CLKID_SYS_I2S_S_A			5263#define CLKID_SYS_RTC				5364#define CLKID_SYS_GE2D				5465#define CLKID_SYS_ISP				5566#define CLKID_SYS_GPV_ISP_NIC			5667#define CLKID_SYS_GPV_CVE_NIC			5768#define CLKID_SYS_MIPI_DSI_HOST			5869#define CLKID_SYS_MIPI_DSI_PHY			5970#define CLKID_SYS_ETH_PHY			6071#define CLKID_SYS_ACODEC			6172#define CLKID_SYS_DWAP				6273#define CLKID_SYS_DOS				6374#define CLKID_SYS_CVE				6475#define CLKID_SYS_VOUT				6576#define CLKID_SYS_VC9000E			6677#define CLKID_SYS_PWM_MN			6778#define CLKID_SYS_SD_EMMC_B			6879#define CLKID_AXI_SYS_NIC			6980#define CLKID_AXI_ISP_NIC			7081#define CLKID_AXI_CVE_NIC			7182#define CLKID_AXI_RAMB				7283#define CLKID_AXI_RAMA				7384#define CLKID_AXI_CPU_DMC			7485#define CLKID_AXI_NIC				7586#define CLKID_AXI_DMA				7687#define CLKID_AXI_MUX_NIC			7788#define CLKID_AXI_CVE				7889#define CLKID_AXI_DEV1_DMC			7990#define CLKID_AXI_DEV0_DMC			8091#define CLKID_AXI_DSP_DMC			8192#define CLKID_12_24M_IN				8293#define CLKID_12M_24M				8394#define CLKID_FCLK_25M_DIV			8495#define CLKID_FCLK_25M				8596#define CLKID_GEN_SEL				8697#define CLKID_GEN_DIV				8798#define CLKID_GEN				8899#define CLKID_SARADC_SEL			89100#define CLKID_SARADC_DIV			90101#define CLKID_SARADC				91102#define CLKID_PWM_A_SEL				92103#define CLKID_PWM_A_DIV				93104#define CLKID_PWM_A				94105#define CLKID_PWM_B_SEL				95106#define CLKID_PWM_B_DIV				96107#define CLKID_PWM_B				97108#define CLKID_PWM_C_SEL				98109#define CLKID_PWM_C_DIV				99110#define CLKID_PWM_C				100111#define CLKID_PWM_D_SEL				101112#define CLKID_PWM_D_DIV				102113#define CLKID_PWM_D				103114#define CLKID_PWM_E_SEL				104115#define CLKID_PWM_E_DIV				105116#define CLKID_PWM_E				106117#define CLKID_PWM_F_SEL				107118#define CLKID_PWM_F_DIV				108119#define CLKID_PWM_F				109120#define CLKID_PWM_G_SEL				110121#define CLKID_PWM_G_DIV				111122#define CLKID_PWM_G				112123#define CLKID_PWM_H_SEL				113124#define CLKID_PWM_H_DIV				114125#define CLKID_PWM_H				115126#define CLKID_PWM_I_SEL				116127#define CLKID_PWM_I_DIV				117128#define CLKID_PWM_I				118129#define CLKID_PWM_J_SEL				119130#define CLKID_PWM_J_DIV				120131#define CLKID_PWM_J				121132#define CLKID_PWM_K_SEL				122133#define CLKID_PWM_K_DIV				123134#define CLKID_PWM_K				124135#define CLKID_PWM_L_SEL				125136#define CLKID_PWM_L_DIV				126137#define CLKID_PWM_L				127138#define CLKID_PWM_M_SEL				128139#define CLKID_PWM_M_DIV				129140#define CLKID_PWM_M				130141#define CLKID_PWM_N_SEL				131142#define CLKID_PWM_N_DIV				132143#define CLKID_PWM_N				133144#define CLKID_SPICC_A_SEL			134145#define CLKID_SPICC_A_DIV			135146#define CLKID_SPICC_A				136147#define CLKID_SPICC_B_SEL			137148#define CLKID_SPICC_B_DIV			138149#define CLKID_SPICC_B				139150#define CLKID_SPIFC_SEL				140151#define CLKID_SPIFC_DIV				141152#define CLKID_SPIFC				142153#define CLKID_SD_EMMC_A_SEL			143154#define CLKID_SD_EMMC_A_DIV			144155#define CLKID_SD_EMMC_A				145156#define CLKID_SD_EMMC_B_SEL			146157#define CLKID_SD_EMMC_B_DIV			147158#define CLKID_SD_EMMC_B				148159#define CLKID_SD_EMMC_C_SEL			149160#define CLKID_SD_EMMC_C_DIV			150161#define CLKID_SD_EMMC_C				151162#define CLKID_TS_DIV				152163#define CLKID_TS				153164#define CLKID_ETH_125M_DIV			154165#define CLKID_ETH_125M				155166#define CLKID_ETH_RMII_DIV			156167#define CLKID_ETH_RMII				157168#define CLKID_MIPI_DSI_MEAS_SEL			158169#define CLKID_MIPI_DSI_MEAS_DIV			159170#define CLKID_MIPI_DSI_MEAS			160171#define CLKID_DSI_PHY_SEL			161172#define CLKID_DSI_PHY_DIV			162173#define CLKID_DSI_PHY				163174#define CLKID_VOUT_MCLK_SEL			164175#define CLKID_VOUT_MCLK_DIV			165176#define CLKID_VOUT_MCLK				166177#define CLKID_VOUT_ENC_SEL			167178#define CLKID_VOUT_ENC_DIV			168179#define CLKID_VOUT_ENC				169180#define CLKID_HCODEC_0_SEL			170181#define CLKID_HCODEC_0_DIV			171182#define CLKID_HCODEC_0				172183#define CLKID_HCODEC_1_SEL			173184#define CLKID_HCODEC_1_DIV			174185#define CLKID_HCODEC_1				175186#define CLKID_HCODEC				176187#define CLKID_VC9000E_ACLK_SEL			177188#define CLKID_VC9000E_ACLK_DIV			178189#define CLKID_VC9000E_ACLK			179190#define CLKID_VC9000E_CORE_SEL			180191#define CLKID_VC9000E_CORE_DIV			181192#define CLKID_VC9000E_CORE			182193#define CLKID_CSI_PHY0_SEL			183194#define CLKID_CSI_PHY0_DIV			184195#define CLKID_CSI_PHY0				185196#define CLKID_DEWARPA_SEL			186197#define CLKID_DEWARPA_DIV			187198#define CLKID_DEWARPA				188199#define CLKID_ISP0_SEL				189200#define CLKID_ISP0_DIV				190201#define CLKID_ISP0				191202#define CLKID_NNA_CORE_SEL			192203#define CLKID_NNA_CORE_DIV			193204#define CLKID_NNA_CORE				194205#define CLKID_GE2D_SEL				195206#define CLKID_GE2D_DIV				196207#define CLKID_GE2D				197208#define CLKID_VAPB_SEL				198209#define CLKID_VAPB_DIV				199210#define CLKID_VAPB				200211 212#endif  /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H */213