41 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */2/*3 * Copyright (c) 2023 Amlogic, Inc. All rights reserved.4 * Author: Chuan Liu <chuan.liu@amlogic.com>5 */6 7#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H8#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H9 10#define CLKID_FCLK_50M_EN 011#define CLKID_FCLK_50M 112#define CLKID_FCLK_DIV2_DIV 213#define CLKID_FCLK_DIV2 314#define CLKID_FCLK_DIV2P5_DIV 415#define CLKID_FCLK_DIV2P5 516#define CLKID_FCLK_DIV3_DIV 617#define CLKID_FCLK_DIV3 718#define CLKID_FCLK_DIV4_DIV 819#define CLKID_FCLK_DIV4 920#define CLKID_FCLK_DIV5_DIV 1021#define CLKID_FCLK_DIV5 1122#define CLKID_FCLK_DIV7_DIV 1223#define CLKID_FCLK_DIV7 1324#define CLKID_GP0_PLL_DCO 1425#define CLKID_GP0_PLL 1526#define CLKID_HIFI_PLL_DCO 1627#define CLKID_HIFI_PLL 1728#define CLKID_MCLK_PLL_DCO 1829#define CLKID_MCLK_PLL_OD 1930#define CLKID_MCLK_PLL 2031#define CLKID_MCLK0_SEL 2132#define CLKID_MCLK0_SEL_EN 2233#define CLKID_MCLK0_DIV 2334#define CLKID_MCLK0 2435#define CLKID_MCLK1_SEL 2536#define CLKID_MCLK1_SEL_EN 2637#define CLKID_MCLK1_DIV 2738#define CLKID_MCLK1 2839 40#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */41