237 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */2/*3 * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.4 * Author: Yu Tu <yu.tu@amlogic.com>5 */6 7#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H8#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H9 10#define CLKID_RTC_32K_CLKIN 011#define CLKID_RTC_32K_DIV 112#define CLKID_RTC_32K_SEL 213#define CLKID_RTC_32K_XATL 314#define CLKID_RTC 415#define CLKID_SYS_CLK_B_SEL 516#define CLKID_SYS_CLK_B_DIV 617#define CLKID_SYS_CLK_B 718#define CLKID_SYS_CLK_A_SEL 819#define CLKID_SYS_CLK_A_DIV 920#define CLKID_SYS_CLK_A 1021#define CLKID_SYS 1122#define CLKID_CECA_32K_CLKIN 1223#define CLKID_CECA_32K_DIV 1324#define CLKID_CECA_32K_SEL_PRE 1425#define CLKID_CECA_32K_SEL 1526#define CLKID_CECA_32K_CLKOUT 1627#define CLKID_CECB_32K_CLKIN 1728#define CLKID_CECB_32K_DIV 1829#define CLKID_CECB_32K_SEL_PRE 1930#define CLKID_CECB_32K_SEL 2031#define CLKID_CECB_32K_CLKOUT 2132#define CLKID_SC_CLK_SEL 2233#define CLKID_SC_CLK_DIV 2334#define CLKID_SC 2435#define CLKID_12_24M 2536#define CLKID_12M_CLK_DIV 2637#define CLKID_12_24M_CLK_SEL 2738#define CLKID_VID_PLL_DIV 2839#define CLKID_VID_PLL_SEL 2940#define CLKID_VID_PLL 3041#define CLKID_VCLK_SEL 3142#define CLKID_VCLK2_SEL 3243#define CLKID_VCLK_INPUT 3344#define CLKID_VCLK2_INPUT 3445#define CLKID_VCLK_DIV 3546#define CLKID_VCLK2_DIV 3647#define CLKID_VCLK 3748#define CLKID_VCLK2 3849#define CLKID_VCLK_DIV1 3950#define CLKID_VCLK_DIV2_EN 4051#define CLKID_VCLK_DIV4_EN 4152#define CLKID_VCLK_DIV6_EN 4253#define CLKID_VCLK_DIV12_EN 4354#define CLKID_VCLK2_DIV1 4455#define CLKID_VCLK2_DIV2_EN 4556#define CLKID_VCLK2_DIV4_EN 4657#define CLKID_VCLK2_DIV6_EN 4758#define CLKID_VCLK2_DIV12_EN 4859#define CLKID_VCLK_DIV2 4960#define CLKID_VCLK_DIV4 5061#define CLKID_VCLK_DIV6 5162#define CLKID_VCLK_DIV12 5263#define CLKID_VCLK2_DIV2 5364#define CLKID_VCLK2_DIV4 5465#define CLKID_VCLK2_DIV6 5566#define CLKID_VCLK2_DIV12 5667#define CLKID_CTS_ENCI_SEL 5768#define CLKID_CTS_ENCP_SEL 5869#define CLKID_CTS_VDAC_SEL 5970#define CLKID_HDMI_TX_SEL 6071#define CLKID_CTS_ENCI 6172#define CLKID_CTS_ENCP 6273#define CLKID_CTS_VDAC 6374#define CLKID_HDMI_TX 6475#define CLKID_HDMI_SEL 6576#define CLKID_HDMI_DIV 6677#define CLKID_HDMI 6778#define CLKID_TS_CLK_DIV 6879#define CLKID_TS 6980#define CLKID_MALI_0_SEL 7081#define CLKID_MALI_0_DIV 7182#define CLKID_MALI_0 7283#define CLKID_MALI_1_SEL 7384#define CLKID_MALI_1_DIV 7485#define CLKID_MALI_1 7586#define CLKID_MALI_SEL 7687#define CLKID_VDEC_P0_SEL 7788#define CLKID_VDEC_P0_DIV 7889#define CLKID_VDEC_P0 7990#define CLKID_VDEC_P1_SEL 8091#define CLKID_VDEC_P1_DIV 8192#define CLKID_VDEC_P1 8293#define CLKID_VDEC_SEL 8394#define CLKID_HEVCF_P0_SEL 8495#define CLKID_HEVCF_P0_DIV 8596#define CLKID_HEVCF_P0 8697#define CLKID_HEVCF_P1_SEL 8798#define CLKID_HEVCF_P1_DIV 8899#define CLKID_HEVCF_P1 89100#define CLKID_HEVCF_SEL 90101#define CLKID_VPU_0_SEL 91102#define CLKID_VPU_0_DIV 92103#define CLKID_VPU_0 93104#define CLKID_VPU_1_SEL 94105#define CLKID_VPU_1_DIV 95106#define CLKID_VPU_1 96107#define CLKID_VPU 97108#define CLKID_VPU_CLKB_TMP_SEL 98109#define CLKID_VPU_CLKB_TMP_DIV 99110#define CLKID_VPU_CLKB_TMP 100111#define CLKID_VPU_CLKB_DIV 101112#define CLKID_VPU_CLKB 102113#define CLKID_VPU_CLKC_P0_SEL 103114#define CLKID_VPU_CLKC_P0_DIV 104115#define CLKID_VPU_CLKC_P0 105116#define CLKID_VPU_CLKC_P1_SEL 106117#define CLKID_VPU_CLKC_P1_DIV 107118#define CLKID_VPU_CLKC_P1 108119#define CLKID_VPU_CLKC_SEL 109120#define CLKID_VAPB_0_SEL 110121#define CLKID_VAPB_0_DIV 111122#define CLKID_VAPB_0 112123#define CLKID_VAPB_1_SEL 113124#define CLKID_VAPB_1_DIV 114125#define CLKID_VAPB_1 115126#define CLKID_VAPB 116127#define CLKID_GE2D 117128#define CLKID_VDIN_MEAS_SEL 118129#define CLKID_VDIN_MEAS_DIV 119130#define CLKID_VDIN_MEAS 120131#define CLKID_SD_EMMC_C_CLK_SEL 121132#define CLKID_SD_EMMC_C_CLK_DIV 122133#define CLKID_SD_EMMC_C 123134#define CLKID_SD_EMMC_A_CLK_SEL 124135#define CLKID_SD_EMMC_A_CLK_DIV 125136#define CLKID_SD_EMMC_A 126137#define CLKID_SD_EMMC_B_CLK_SEL 127138#define CLKID_SD_EMMC_B_CLK_DIV 128139#define CLKID_SD_EMMC_B 129140#define CLKID_SPICC0_SEL 130141#define CLKID_SPICC0_DIV 131142#define CLKID_SPICC0_EN 132143#define CLKID_PWM_A_SEL 133144#define CLKID_PWM_A_DIV 134145#define CLKID_PWM_A 135146#define CLKID_PWM_B_SEL 136147#define CLKID_PWM_B_DIV 137148#define CLKID_PWM_B 138149#define CLKID_PWM_C_SEL 139150#define CLKID_PWM_C_DIV 140151#define CLKID_PWM_C 141152#define CLKID_PWM_D_SEL 142153#define CLKID_PWM_D_DIV 143154#define CLKID_PWM_D 144155#define CLKID_PWM_E_SEL 145156#define CLKID_PWM_E_DIV 146157#define CLKID_PWM_E 147158#define CLKID_PWM_F_SEL 148159#define CLKID_PWM_F_DIV 149160#define CLKID_PWM_F 150161#define CLKID_PWM_G_SEL 151162#define CLKID_PWM_G_DIV 152163#define CLKID_PWM_G 153164#define CLKID_PWM_H_SEL 154165#define CLKID_PWM_H_DIV 155166#define CLKID_PWM_H 156167#define CLKID_PWM_I_SEL 157168#define CLKID_PWM_I_DIV 158169#define CLKID_PWM_I 159170#define CLKID_PWM_J_SEL 160171#define CLKID_PWM_J_DIV 161172#define CLKID_PWM_J 162173#define CLKID_SARADC_SEL 163174#define CLKID_SARADC_DIV 164175#define CLKID_SARADC 165176#define CLKID_GEN_SEL 166177#define CLKID_GEN_DIV 167178#define CLKID_GEN 168179#define CLKID_DDR 169180#define CLKID_DOS 170181#define CLKID_ETHPHY 171182#define CLKID_MALI 172183#define CLKID_AOCPU 173184#define CLKID_AUCPU 174185#define CLKID_CEC 175186#define CLKID_SDEMMC_A 176187#define CLKID_SDEMMC_B 177188#define CLKID_NAND 178189#define CLKID_SMARTCARD 179190#define CLKID_ACODEC 180191#define CLKID_SPIFC 181192#define CLKID_MSR 182193#define CLKID_IR_CTRL 183194#define CLKID_AUDIO 184195#define CLKID_ETH 185196#define CLKID_UART_A 186197#define CLKID_UART_B 187198#define CLKID_UART_C 188199#define CLKID_UART_D 189200#define CLKID_UART_E 190201#define CLKID_AIFIFO 191202#define CLKID_TS_DDR 192203#define CLKID_TS_PLL 193204#define CLKID_G2D 194205#define CLKID_SPICC0 195206#define CLKID_SPICC1 196207#define CLKID_USB 197208#define CLKID_I2C_M_A 198209#define CLKID_I2C_M_B 199210#define CLKID_I2C_M_C 200211#define CLKID_I2C_M_D 201212#define CLKID_I2C_M_E 202213#define CLKID_HDMITX_APB 203214#define CLKID_I2C_S_A 204215#define CLKID_USB1_TO_DDR 205216#define CLKID_HDCP22 206217#define CLKID_MMC_APB 207218#define CLKID_RSA 208219#define CLKID_CPU_DEBUG 209220#define CLKID_VPU_INTR 210221#define CLKID_DEMOD 211222#define CLKID_SAR_ADC 212223#define CLKID_GIC 213224#define CLKID_PWM_AB 214225#define CLKID_PWM_CD 215226#define CLKID_PWM_EF 216227#define CLKID_PWM_GH 217228#define CLKID_PWM_IJ 218229#define CLKID_HDCP22_ESMCLK_SEL 219230#define CLKID_HDCP22_ESMCLK_DIV 220231#define CLKID_HDCP22_ESMCLK 221232#define CLKID_HDCP22_SKPCLK_SEL 222233#define CLKID_HDCP22_SKPCLK_DIV 223234#define CLKID_HDCP22_SKPCLK 224235 236#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */237