44 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */2/*3 * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.4 * Author: Yu Tu <yu.tu@amlogic.com>5 */6 7#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H8#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H9 10#define CLKID_FIXED_PLL_DCO 011#define CLKID_FIXED_PLL 112#define CLKID_FCLK_DIV2_DIV 213#define CLKID_FCLK_DIV2 314#define CLKID_FCLK_DIV3_DIV 415#define CLKID_FCLK_DIV3 516#define CLKID_FCLK_DIV4_DIV 617#define CLKID_FCLK_DIV4 718#define CLKID_FCLK_DIV5_DIV 819#define CLKID_FCLK_DIV5 920#define CLKID_FCLK_DIV7_DIV 1021#define CLKID_FCLK_DIV7 1122#define CLKID_FCLK_DIV2P5_DIV 1223#define CLKID_FCLK_DIV2P5 1324#define CLKID_GP0_PLL_DCO 1425#define CLKID_GP0_PLL 1526#define CLKID_HIFI_PLL_DCO 1627#define CLKID_HIFI_PLL 1728#define CLKID_HDMI_PLL_DCO 1829#define CLKID_HDMI_PLL_OD 1930#define CLKID_HDMI_PLL 2031#define CLKID_MPLL_50M_DIV 2132#define CLKID_MPLL_50M 2233#define CLKID_MPLL_PREDIV 2334#define CLKID_MPLL0_DIV 2435#define CLKID_MPLL0 2536#define CLKID_MPLL1_DIV 2637#define CLKID_MPLL1 2738#define CLKID_MPLL2_DIV 2839#define CLKID_MPLL2 2940#define CLKID_MPLL3_DIV 3041#define CLKID_MPLL3 3142 43#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */44