149 lines · c
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */2/*3 * Meson-AXG clock tree IDs4 *5 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.6 */7 8#ifndef __AXG_CLKC_H9#define __AXG_CLKC_H10 11#define CLKID_SYS_PLL 012#define CLKID_FIXED_PLL 113#define CLKID_FCLK_DIV2 214#define CLKID_FCLK_DIV3 315#define CLKID_FCLK_DIV4 416#define CLKID_FCLK_DIV5 517#define CLKID_FCLK_DIV7 618#define CLKID_GP0_PLL 719#define CLKID_MPEG_SEL 820#define CLKID_MPEG_DIV 921#define CLKID_CLK81 1022#define CLKID_MPLL0 1123#define CLKID_MPLL1 1224#define CLKID_MPLL2 1325#define CLKID_MPLL3 1426#define CLKID_DDR 1527#define CLKID_AUDIO_LOCKER 1628#define CLKID_MIPI_DSI_HOST 1729#define CLKID_ISA 1830#define CLKID_PL301 1931#define CLKID_PERIPHS 2032#define CLKID_SPICC0 2133#define CLKID_I2C 2234#define CLKID_RNG0 2335#define CLKID_UART0 2436#define CLKID_MIPI_DSI_PHY 2537#define CLKID_SPICC1 2638#define CLKID_PCIE_A 2739#define CLKID_PCIE_B 2840#define CLKID_HIU_IFACE 2941#define CLKID_ASSIST_MISC 3042#define CLKID_SD_EMMC_B 3143#define CLKID_SD_EMMC_C 3244#define CLKID_DMA 3345#define CLKID_SPI 3446#define CLKID_AUDIO 3547#define CLKID_ETH 3648#define CLKID_UART1 3749#define CLKID_G2D 3850#define CLKID_USB0 3951#define CLKID_USB1 4052#define CLKID_RESET 4153#define CLKID_USB 4254#define CLKID_AHB_ARB0 4355#define CLKID_EFUSE 4456#define CLKID_BOOT_ROM 4557#define CLKID_AHB_DATA_BUS 4658#define CLKID_AHB_CTRL_BUS 4759#define CLKID_USB1_DDR_BRIDGE 4860#define CLKID_USB0_DDR_BRIDGE 4961#define CLKID_MMC_PCLK 5062#define CLKID_VPU_INTR 5163#define CLKID_SEC_AHB_AHB3_BRIDGE 5264#define CLKID_GIC 5365#define CLKID_AO_MEDIA_CPU 5466#define CLKID_AO_AHB_SRAM 5567#define CLKID_AO_AHB_BUS 5668#define CLKID_AO_IFACE 5769#define CLKID_AO_I2C 5870#define CLKID_SD_EMMC_B_CLK0 5971#define CLKID_SD_EMMC_C_CLK0 6072#define CLKID_SD_EMMC_B_CLK0_SEL 6173#define CLKID_SD_EMMC_B_CLK0_DIV 6274#define CLKID_SD_EMMC_C_CLK0_SEL 6375#define CLKID_SD_EMMC_C_CLK0_DIV 6476#define CLKID_MPLL0_DIV 6577#define CLKID_MPLL1_DIV 6678#define CLKID_MPLL2_DIV 6779#define CLKID_MPLL3_DIV 6880#define CLKID_HIFI_PLL 6981#define CLKID_MPLL_PREDIV 7082#define CLKID_FCLK_DIV2_DIV 7183#define CLKID_FCLK_DIV3_DIV 7284#define CLKID_FCLK_DIV4_DIV 7385#define CLKID_FCLK_DIV5_DIV 7486#define CLKID_FCLK_DIV7_DIV 7587#define CLKID_PCIE_PLL 7688#define CLKID_PCIE_MUX 7789#define CLKID_PCIE_REF 7890#define CLKID_PCIE_CML_EN0 7991#define CLKID_PCIE_CML_EN1 8092#define CLKID_GEN_CLK_SEL 8293#define CLKID_GEN_CLK_DIV 8394#define CLKID_GEN_CLK 8495#define CLKID_SYS_PLL_DCO 8596#define CLKID_FIXED_PLL_DCO 8697#define CLKID_GP0_PLL_DCO 8798#define CLKID_HIFI_PLL_DCO 8899#define CLKID_PCIE_PLL_DCO 89100#define CLKID_PCIE_PLL_OD 90101#define CLKID_VPU_0_DIV 91102#define CLKID_VPU_0_SEL 92103#define CLKID_VPU_0 93104#define CLKID_VPU_1_DIV 94105#define CLKID_VPU_1_SEL 95106#define CLKID_VPU_1 96107#define CLKID_VPU 97108#define CLKID_VAPB_0_DIV 98109#define CLKID_VAPB_0_SEL 99110#define CLKID_VAPB_0 100111#define CLKID_VAPB_1_DIV 101112#define CLKID_VAPB_1_SEL 102113#define CLKID_VAPB_1 103114#define CLKID_VAPB_SEL 104115#define CLKID_VAPB 105116#define CLKID_VCLK 106117#define CLKID_VCLK2 107118#define CLKID_VCLK_SEL 108119#define CLKID_VCLK2_SEL 109120#define CLKID_VCLK_INPUT 110121#define CLKID_VCLK2_INPUT 111122#define CLKID_VCLK_DIV 112123#define CLKID_VCLK2_DIV 113124#define CLKID_VCLK_DIV2_EN 114125#define CLKID_VCLK_DIV4_EN 115126#define CLKID_VCLK_DIV6_EN 116127#define CLKID_VCLK_DIV12_EN 117128#define CLKID_VCLK2_DIV2_EN 118129#define CLKID_VCLK2_DIV4_EN 119130#define CLKID_VCLK2_DIV6_EN 120131#define CLKID_VCLK2_DIV12_EN 121132#define CLKID_VCLK_DIV1 122133#define CLKID_VCLK_DIV2 123134#define CLKID_VCLK_DIV4 124135#define CLKID_VCLK_DIV6 125136#define CLKID_VCLK_DIV12 126137#define CLKID_VCLK2_DIV1 127138#define CLKID_VCLK2_DIV2 128139#define CLKID_VCLK2_DIV4 129140#define CLKID_VCLK2_DIV6 130141#define CLKID_VCLK2_DIV12 131142#define CLKID_CTS_ENCL_SEL 132143#define CLKID_CTS_ENCL 133144#define CLKID_VDIN_MEAS_SEL 134145#define CLKID_VDIN_MEAS_DIV 135146#define CLKID_VDIN_MEAS 136147 148#endif /* __AXG_CLKC_H */149