36 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * ARTPEC-6 clock controller indexes4 *5 * Copyright 2016 Axis Communications AB.6 */7 8#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H9#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H10 11#define ARTPEC6_CLK_CPU 012#define ARTPEC6_CLK_CPU_PERIPH 113#define ARTPEC6_CLK_NAND_CLKA 214#define ARTPEC6_CLK_NAND_CLKB 315#define ARTPEC6_CLK_ETH_ACLK 416#define ARTPEC6_CLK_DMA_ACLK 517#define ARTPEC6_CLK_PTP_REF 618#define ARTPEC6_CLK_SD_PCLK 719#define ARTPEC6_CLK_SD_IMCLK 820#define ARTPEC6_CLK_I2S_HST 921#define ARTPEC6_CLK_I2S0_CLK 1022#define ARTPEC6_CLK_I2S1_CLK 1123#define ARTPEC6_CLK_UART_PCLK 1224#define ARTPEC6_CLK_UART_REFCLK 1325#define ARTPEC6_CLK_I2C 1426#define ARTPEC6_CLK_SPI_PCLK 1527#define ARTPEC6_CLK_SPI_SSPCLK 1628#define ARTPEC6_CLK_SYS_TIMER 1729#define ARTPEC6_CLK_FRACDIV_IN 1830#define ARTPEC6_CLK_DBG_PCLK 1931 32/* This must be the highest clock index plus one. */33#define ARTPEC6_CLK_NUMCLOCKS 2034 35#endif36