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1/*2 * BSD LICENSE3 *4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.5 *6 * Redistribution and use in source and binary forms, with or without7 * modification, are permitted provided that the following conditions8 * are met:9 *10 * * Redistributions of source code must retain the above copyright11 * notice, this list of conditions and the following disclaimer.12 * * Redistributions in binary form must reproduce the above copyright13 * notice, this list of conditions and the following disclaimer in14 * the documentation and/or other materials provided with the15 * distribution.16 * * Neither the name of Broadcom Corporation nor the names of its17 * contributors may be used to endorse or promote products derived18 * from this software without specific prior written permission.19 *20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.31 */32 33#ifndef _CLOCK_BCM_NS2_H34#define _CLOCK_BCM_NS2_H35 36/* GENPLL SCR clock channel ID */37#define BCM_NS2_GENPLL_SCR 038#define BCM_NS2_GENPLL_SCR_SCR_CLK 139#define BCM_NS2_GENPLL_SCR_FS_CLK 240#define BCM_NS2_GENPLL_SCR_AUDIO_CLK 341#define BCM_NS2_GENPLL_SCR_CH3_UNUSED 442#define BCM_NS2_GENPLL_SCR_CH4_UNUSED 543#define BCM_NS2_GENPLL_SCR_CH5_UNUSED 644 45/* GENPLL SW clock channel ID */46#define BCM_NS2_GENPLL_SW 047#define BCM_NS2_GENPLL_SW_RPE_CLK 148#define BCM_NS2_GENPLL_SW_250_CLK 249#define BCM_NS2_GENPLL_SW_NIC_CLK 350#define BCM_NS2_GENPLL_SW_CHIMP_CLK 451#define BCM_NS2_GENPLL_SW_PORT_CLK 552#define BCM_NS2_GENPLL_SW_SDIO_CLK 653 54/* LCPLL DDR clock channel ID */55#define BCM_NS2_LCPLL_DDR 056#define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK 157#define BCM_NS2_LCPLL_DDR_DDR_CLK 258#define BCM_NS2_LCPLL_DDR_CH2_UNUSED 359#define BCM_NS2_LCPLL_DDR_CH3_UNUSED 460#define BCM_NS2_LCPLL_DDR_CH4_UNUSED 561#define BCM_NS2_LCPLL_DDR_CH5_UNUSED 662 63/* LCPLL PORTS clock channel ID */64#define BCM_NS2_LCPLL_PORTS 065#define BCM_NS2_LCPLL_PORTS_WAN_CLK 166#define BCM_NS2_LCPLL_PORTS_RGMII_CLK 267#define BCM_NS2_LCPLL_PORTS_CH2_UNUSED 368#define BCM_NS2_LCPLL_PORTS_CH3_UNUSED 469#define BCM_NS2_LCPLL_PORTS_CH4_UNUSED 570#define BCM_NS2_LCPLL_PORTS_CH5_UNUSED 671 72#endif /* _CLOCK_BCM_NS2_H */73