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1/*2 * BSD LICENSE3 *4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.5 *6 * Redistribution and use in source and binary forms, with or without7 * modification, are permitted provided that the following conditions8 * are met:9 *10 * * Redistributions of source code must retain the above copyright11 * notice, this list of conditions and the following disclaimer.12 * * Redistributions in binary form must reproduce the above copyright13 * notice, this list of conditions and the following disclaimer in14 * the documentation and/or other materials provided with the15 * distribution.16 * * Neither the name of Broadcom Corporation nor the names of its17 * contributors may be used to endorse or promote products derived18 * from this software without specific prior written permission.19 *20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.31 */32 33#ifndef _CLOCK_BCM_NSP_H34#define _CLOCK_BCM_NSP_H35 36/* GENPLL clock channel ID */37#define BCM_NSP_GENPLL 038#define BCM_NSP_GENPLL_PHY_CLK 139#define BCM_NSP_GENPLL_ENET_SW_CLK 240#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 341#define BCM_NSP_GENPLL_IPROCFAST_CLK 442#define BCM_NSP_GENPLL_SATA1_CLK 543#define BCM_NSP_GENPLL_SATA2_CLK 644 45/* LCPLL0 clock channel ID */46#define BCM_NSP_LCPLL0 047#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 148#define BCM_NSP_LCPLL0_SDIO_CLK 249#define BCM_NSP_LCPLL0_DDR_PHY_CLK 350 51#endif /* _CLOCK_BCM_NSP_H */52