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1/*2 * BSD LICENSE3 *4 * Copyright(c) 2017 Broadcom. All rights reserved.5 *6 * Redistribution and use in source and binary forms, with or without7 * modification, are permitted provided that the following conditions8 * are met:9 *10 * * Redistributions of source code must retain the above copyright11 * notice, this list of conditions and the following disclaimer.12 * * Redistributions in binary form must reproduce the above copyright13 * notice, this list of conditions and the following disclaimer in14 * the documentation and/or other materials provided with the15 * distribution.16 * * Neither the name of Broadcom Corporation nor the names of its17 * contributors may be used to endorse or promote products derived18 * from this software without specific prior written permission.19 *20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.31 */32 33#ifndef _CLOCK_BCM_SR_H34#define _CLOCK_BCM_SR_H35 36/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */37#define BCM_SR_GENPLL0 038#define BCM_SR_GENPLL0_125M_CLK 139#define BCM_SR_GENPLL0_SCR_CLK 240#define BCM_SR_GENPLL0_250M_CLK 341#define BCM_SR_GENPLL0_PCIE_AXI_CLK 442#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 543#define BCM_SR_GENPLL0_PAXC_AXI_CLK 644 45/* GENPLL 1 clock channel ID MHB PCIE NITRO */46#define BCM_SR_GENPLL1 047#define BCM_SR_GENPLL1_PCIE_TL_CLK 148#define BCM_SR_GENPLL1_MHB_APB_CLK 249 50/* GENPLL 2 clock channel ID NITRO MHB*/51#define BCM_SR_GENPLL2 052#define BCM_SR_GENPLL2_NIC_CLK 153#define BCM_SR_GENPLL2_TS_500_CLK 254#define BCM_SR_GENPLL2_125_NITRO_CLK 355#define BCM_SR_GENPLL2_CHIMP_CLK 456#define BCM_SR_GENPLL2_NIC_FLASH_CLK 557#define BCM_SR_GENPLL2_FS4_CLK 658 59/* GENPLL 3 HSLS clock channel ID */60#define BCM_SR_GENPLL3 061#define BCM_SR_GENPLL3_HSLS_CLK 162#define BCM_SR_GENPLL3_SDIO_CLK 263 64/* GENPLL 4 SCR clock channel ID */65#define BCM_SR_GENPLL4 066#define BCM_SR_GENPLL4_CCN_CLK 167#define BCM_SR_GENPLL4_TPIU_PLL_CLK 268#define BCM_SR_GENPLL4_NOC_CLK 369#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 470#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 571 72/* GENPLL 5 FS4 clock channel ID */73#define BCM_SR_GENPLL5 074#define BCM_SR_GENPLL5_FS4_HF_CLK 175#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 276#define BCM_SR_GENPLL5_RAID_AE_CLK 377 78/* GENPLL 6 NITRO clock channel ID */79#define BCM_SR_GENPLL6 080#define BCM_SR_GENPLL6_48_USB_CLK 181 82/* LCPLL0 clock channel ID */83#define BCM_SR_LCPLL0 084#define BCM_SR_LCPLL0_SATA_REFP_CLK 185#define BCM_SR_LCPLL0_SATA_REFN_CLK 286#define BCM_SR_LCPLL0_SATA_350_CLK 387#define BCM_SR_LCPLL0_SATA_500_CLK 488 89/* LCPLL1 clock channel ID */90#define BCM_SR_LCPLL1 091#define BCM_SR_LCPLL1_WAN_CLK 192#define BCM_SR_LCPLL1_USB_REF_CLK 293#define BCM_SR_LCPLL1_CRMU_TS_CLK 394 95/* LCPLL PCIE clock channel ID */96#define BCM_SR_LCPLL_PCIE 097#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 198 99/* GENPLL EMEM0 clock channel ID */100#define BCM_SR_EMEMPLL0 0101#define BCM_SR_EMEMPLL0_EMEM_CLK 1102 103/* GENPLL EMEM0 clock channel ID */104#define BCM_SR_EMEMPLL1 0105#define BCM_SR_EMEMPLL1_EMEM_CLK 1106 107/* GENPLL EMEM0 clock channel ID */108#define BCM_SR_EMEMPLL2 0109#define BCM_SR_EMEMPLL2_EMEM_CLK 1110 111#endif /* _CLOCK_BCM_SR_H */112