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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.4 * Author: Tomasz Figa <t.figa@samsung.com>5 *6 * Device Tree binding constants for Samsung Exynos3250 clock controllers.7 */8 9#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H10#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H11 12/*13 * Let each exported clock get a unique index, which is used on DT-enabled14 * platforms to lookup the clock from a clock specifier. These indices are15 * therefore considered an ABI and so must not be changed. This implies16 * that new clocks should be added either in free spaces between clock groups17 * or at the end.18 */19 20 21/*22 * Main CMU23 */24 25#define CLK_OSCSEL 126#define CLK_FIN_PLL 227#define CLK_FOUT_APLL 328#define CLK_FOUT_VPLL 429#define CLK_FOUT_UPLL 530#define CLK_FOUT_MPLL 631#define CLK_ARM_CLK 732 33/* Muxes */34#define CLK_MOUT_MPLL_USER_L 1635#define CLK_MOUT_GDL 1736#define CLK_MOUT_MPLL_USER_R 1837#define CLK_MOUT_GDR 1938#define CLK_MOUT_EBI 2039#define CLK_MOUT_ACLK_200 2140#define CLK_MOUT_ACLK_160 2241#define CLK_MOUT_ACLK_100 2342#define CLK_MOUT_ACLK_266_1 2443#define CLK_MOUT_ACLK_266_0 2544#define CLK_MOUT_ACLK_266 2645#define CLK_MOUT_VPLL 2746#define CLK_MOUT_EPLL_USER 2847#define CLK_MOUT_EBI_1 2948#define CLK_MOUT_UPLL 3049#define CLK_MOUT_ACLK_400_MCUISP_SUB 3150#define CLK_MOUT_MPLL 3251#define CLK_MOUT_ACLK_400_MCUISP 3352#define CLK_MOUT_VPLLSRC 3453#define CLK_MOUT_CAM1 3554#define CLK_MOUT_CAM_BLK 3655#define CLK_MOUT_MFC 3756#define CLK_MOUT_MFC_1 3857#define CLK_MOUT_MFC_0 3958#define CLK_MOUT_G3D 4059#define CLK_MOUT_G3D_1 4160#define CLK_MOUT_G3D_0 4261#define CLK_MOUT_MIPI0 4362#define CLK_MOUT_FIMD0 4463#define CLK_MOUT_UART_ISP 4564#define CLK_MOUT_SPI1_ISP 4665#define CLK_MOUT_SPI0_ISP 4766#define CLK_MOUT_TSADC 4867#define CLK_MOUT_MMC1 4968#define CLK_MOUT_MMC0 5069#define CLK_MOUT_UART1 5170#define CLK_MOUT_UART0 5271#define CLK_MOUT_SPI1 5372#define CLK_MOUT_SPI0 5473#define CLK_MOUT_AUDIO 5574#define CLK_MOUT_MPLL_USER_C 5675#define CLK_MOUT_HPM 5776#define CLK_MOUT_CORE 5877#define CLK_MOUT_APLL 5978#define CLK_MOUT_ACLK_266_SUB 6079#define CLK_MOUT_UART2 6180#define CLK_MOUT_MMC2 6281 82/* Dividers */83#define CLK_DIV_GPL 6484#define CLK_DIV_GDL 6585#define CLK_DIV_GPR 6686#define CLK_DIV_GDR 6787#define CLK_DIV_MPLL_PRE 6888#define CLK_DIV_ACLK_400_MCUISP 6989#define CLK_DIV_EBI 7090#define CLK_DIV_ACLK_200 7191#define CLK_DIV_ACLK_160 7292#define CLK_DIV_ACLK_100 7393#define CLK_DIV_ACLK_266 7494#define CLK_DIV_CAM1 7595#define CLK_DIV_CAM_BLK 7696#define CLK_DIV_MFC 7797#define CLK_DIV_G3D 7898#define CLK_DIV_MIPI0_PRE 7999#define CLK_DIV_MIPI0 80100#define CLK_DIV_FIMD0 81101#define CLK_DIV_UART_ISP 82102#define CLK_DIV_SPI1_ISP_PRE 83103#define CLK_DIV_SPI1_ISP 84104#define CLK_DIV_SPI0_ISP_PRE 85105#define CLK_DIV_SPI0_ISP 86106#define CLK_DIV_TSADC_PRE 87107#define CLK_DIV_TSADC 88108#define CLK_DIV_MMC1_PRE 89109#define CLK_DIV_MMC1 90110#define CLK_DIV_MMC0_PRE 91111#define CLK_DIV_MMC0 92112#define CLK_DIV_UART1 93113#define CLK_DIV_UART0 94114#define CLK_DIV_SPI1_PRE 95115#define CLK_DIV_SPI1 96116#define CLK_DIV_SPI0_PRE 97117#define CLK_DIV_SPI0 98118#define CLK_DIV_PCM 99119#define CLK_DIV_AUDIO 100120#define CLK_DIV_I2S 101121#define CLK_DIV_CORE2 102122#define CLK_DIV_APLL 103123#define CLK_DIV_PCLK_DBG 104124#define CLK_DIV_ATB 105125#define CLK_DIV_COREM 106126#define CLK_DIV_CORE 107127#define CLK_DIV_HPM 108128#define CLK_DIV_COPY 109129#define CLK_DIV_UART2 110130#define CLK_DIV_MMC2_PRE 111131#define CLK_DIV_MMC2 112132 133/* Gates */134#define CLK_ASYNC_G3D 128135#define CLK_ASYNC_MFCL 129136#define CLK_PPMULEFT 130137#define CLK_GPIO_LEFT 131138#define CLK_ASYNC_ISPMX 132139#define CLK_ASYNC_FSYSD 133140#define CLK_ASYNC_LCD0X 134141#define CLK_ASYNC_CAMX 135142#define CLK_PPMURIGHT 136143#define CLK_GPIO_RIGHT 137144#define CLK_MONOCNT 138145#define CLK_TZPC6 139146#define CLK_PROVISIONKEY1 140147#define CLK_PROVISIONKEY0 141148#define CLK_CMU_ISPPART 142149#define CLK_TMU_APBIF 143150#define CLK_KEYIF 144151#define CLK_RTC 145152#define CLK_WDT 146153#define CLK_MCT 147154#define CLK_SECKEY 148155#define CLK_TZPC5 149156#define CLK_TZPC4 150157#define CLK_TZPC3 151158#define CLK_TZPC2 152159#define CLK_TZPC1 153160#define CLK_TZPC0 154161#define CLK_CMU_COREPART 155162#define CLK_CMU_TOPPART 156163#define CLK_PMU_APBIF 157164#define CLK_SYSREG 158165#define CLK_CHIP_ID 159166#define CLK_QEJPEG 160167#define CLK_PIXELASYNCM1 161168#define CLK_PIXELASYNCM0 162169#define CLK_PPMUCAMIF 163170#define CLK_QEM2MSCALER 164171#define CLK_QEGSCALER1 165172#define CLK_QEGSCALER0 166173#define CLK_SMMUJPEG 167174#define CLK_SMMUM2M2SCALER 168175#define CLK_SMMUGSCALER1 169176#define CLK_SMMUGSCALER0 170177#define CLK_JPEG 171178#define CLK_M2MSCALER 172179#define CLK_GSCALER1 173180#define CLK_GSCALER0 174181#define CLK_QEMFC 175182#define CLK_PPMUMFC_L 176183#define CLK_SMMUMFC_L 177184#define CLK_MFC 178185#define CLK_SMMUG3D 179186#define CLK_QEG3D 180187#define CLK_PPMUG3D 181188#define CLK_G3D 182189#define CLK_QE_CH1_LCD 183190#define CLK_QE_CH0_LCD 184191#define CLK_PPMULCD0 185192#define CLK_SMMUFIMD0 186193#define CLK_DSIM0 187194#define CLK_FIMD0 188195#define CLK_CAM1 189196#define CLK_UART_ISP_TOP 190197#define CLK_SPI1_ISP_TOP 191198#define CLK_SPI0_ISP_TOP 192199#define CLK_TSADC 193200#define CLK_PPMUFILE 194201#define CLK_USBOTG 195202#define CLK_USBHOST 196203#define CLK_SROMC 197204#define CLK_SDMMC1 198205#define CLK_SDMMC0 199206#define CLK_PDMA1 200207#define CLK_PDMA0 201208#define CLK_PWM 202209#define CLK_PCM 203210#define CLK_I2S 204211#define CLK_SPI1 205212#define CLK_SPI0 206213#define CLK_I2C7 207214#define CLK_I2C6 208215#define CLK_I2C5 209216#define CLK_I2C4 210217#define CLK_I2C3 211218#define CLK_I2C2 212219#define CLK_I2C1 213220#define CLK_I2C0 214221#define CLK_UART1 215222#define CLK_UART0 216223#define CLK_BLOCK_LCD 217224#define CLK_BLOCK_G3D 218225#define CLK_BLOCK_MFC 219226#define CLK_BLOCK_CAM 220227#define CLK_SMIES 221228#define CLK_UART2 222229#define CLK_SDMMC2 223230 231/* Special clocks */232#define CLK_SCLK_JPEG 224233#define CLK_SCLK_M2MSCALER 225234#define CLK_SCLK_GSCALER1 226235#define CLK_SCLK_GSCALER0 227236#define CLK_SCLK_MFC 228237#define CLK_SCLK_G3D 229238#define CLK_SCLK_MIPIDPHY2L 230239#define CLK_SCLK_MIPI0 231240#define CLK_SCLK_FIMD0 232241#define CLK_SCLK_CAM1 233242#define CLK_SCLK_UART_ISP 234243#define CLK_SCLK_SPI1_ISP 235244#define CLK_SCLK_SPI0_ISP 236245#define CLK_SCLK_UPLL 237246#define CLK_SCLK_TSADC 238247#define CLK_SCLK_EBI 239248#define CLK_SCLK_MMC1 240249#define CLK_SCLK_MMC0 241250#define CLK_SCLK_I2S 242251#define CLK_SCLK_PCM 243252#define CLK_SCLK_SPI1 244253#define CLK_SCLK_SPI0 245254#define CLK_SCLK_UART1 246255#define CLK_SCLK_UART0 247256#define CLK_SCLK_UART2 248257#define CLK_SCLK_MMC2 249258 259/*260 * CMU DMC261 */262 263#define CLK_FOUT_BPLL 1264#define CLK_FOUT_EPLL 2265 266/* Muxes */267#define CLK_MOUT_MPLL_MIF 8268#define CLK_MOUT_BPLL 9269#define CLK_MOUT_DPHY 10270#define CLK_MOUT_DMC_BUS 11271#define CLK_MOUT_EPLL 12272 273/* Dividers */274#define CLK_DIV_DMC 16275#define CLK_DIV_DPHY 17276#define CLK_DIV_DMC_PRE 18277#define CLK_DIV_DMCP 19278#define CLK_DIV_DMCD 20279 280/*281 * CMU ISP282 */283 284/* Dividers */285 286#define CLK_DIV_ISP1 1287#define CLK_DIV_ISP0 2288#define CLK_DIV_MCUISP1 3289#define CLK_DIV_MCUISP0 4290#define CLK_DIV_MPWM 5291 292/* Gates */293 294#define CLK_UART_ISP 8295#define CLK_WDT_ISP 9296#define CLK_PWM_ISP 10297#define CLK_I2C1_ISP 11298#define CLK_I2C0_ISP 12299#define CLK_MPWM_ISP 13300#define CLK_MCUCTL_ISP 14301#define CLK_PPMUISPX 15302#define CLK_PPMUISPMX 16303#define CLK_QE_LITE1 17304#define CLK_QE_LITE0 18305#define CLK_QE_FD 19306#define CLK_QE_DRC 20307#define CLK_QE_ISP 21308#define CLK_CSIS1 22309#define CLK_SMMU_LITE1 23310#define CLK_SMMU_LITE0 24311#define CLK_SMMU_FD 25312#define CLK_SMMU_DRC 26313#define CLK_SMMU_ISP 27314#define CLK_GICISP 28315#define CLK_CSIS0 29316#define CLK_MCUISP 30317#define CLK_LITE1 31318#define CLK_LITE0 32319#define CLK_FD 33320#define CLK_DRC 34321#define CLK_ISP 35322#define CLK_QE_ISPCX 36323#define CLK_QE_SCALERP 37324#define CLK_QE_SCALERC 38325#define CLK_SMMU_SCALERP 39326#define CLK_SMMU_SCALERC 40327#define CLK_SCALERP 41328#define CLK_SCALERC 42329#define CLK_SPI1_ISP 43330#define CLK_SPI0_ISP 44331#define CLK_SMMU_ISPCX 45332#define CLK_ASYNCAXIM 46333#define CLK_SCLK_MPWM_ISP 47334 335#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */336