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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.4 * Author: Andrzej Hajda <a.hajda@samsung.com>5 *6 * Device Tree binding constants for Exynos4 clock controller.7 */8 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H10#define _DT_BINDINGS_CLOCK_EXYNOS_4_H11 12/* core clocks */13#define CLK_XXTI 114#define CLK_XUSBXTI 215#define CLK_FIN_PLL 316#define CLK_FOUT_APLL 417#define CLK_FOUT_MPLL 518#define CLK_FOUT_EPLL 619#define CLK_FOUT_VPLL 720#define CLK_SCLK_APLL 821#define CLK_SCLK_MPLL 922#define CLK_SCLK_EPLL 1023#define CLK_SCLK_VPLL 1124#define CLK_ARM_CLK 1225#define CLK_ACLK200 1326#define CLK_ACLK100 1427#define CLK_ACLK160 1528#define CLK_ACLK133 1629#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */30#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */31#define CLK_MOUT_CORE 1932#define CLK_MOUT_APLL 2033#define CLK_SCLK_HDMIPHY 2234#define CLK_OUT_DMC 2335#define CLK_OUT_TOP 2436#define CLK_OUT_LEFTBUS 2537#define CLK_OUT_RIGHTBUS 2638#define CLK_OUT_CPU 2739 40/* gate for special clocks (sclk) */41#define CLK_SCLK_FIMC0 12842#define CLK_SCLK_FIMC1 12943#define CLK_SCLK_FIMC2 13044#define CLK_SCLK_FIMC3 13145#define CLK_SCLK_CAM0 13246#define CLK_SCLK_CAM1 13347#define CLK_SCLK_CSIS0 13448#define CLK_SCLK_CSIS1 13549#define CLK_SCLK_HDMI 13650#define CLK_SCLK_MIXER 13751#define CLK_SCLK_DAC 13852#define CLK_SCLK_PIXEL 13953#define CLK_SCLK_FIMD0 14054#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */55#define CLK_SCLK_MDNIE_PWM0 14256#define CLK_SCLK_MIPI0 14357#define CLK_SCLK_AUDIO0 14458#define CLK_SCLK_MMC0 14559#define CLK_SCLK_MMC1 14660#define CLK_SCLK_MMC2 14761#define CLK_SCLK_MMC3 14862#define CLK_SCLK_MMC4 14963#define CLK_SCLK_SATA 150 /* Exynos4210 only */64#define CLK_SCLK_UART0 15165#define CLK_SCLK_UART1 15266#define CLK_SCLK_UART2 15367#define CLK_SCLK_UART3 15468#define CLK_SCLK_UART4 15569#define CLK_SCLK_AUDIO1 15670#define CLK_SCLK_AUDIO2 15771#define CLK_SCLK_SPDIF 15872#define CLK_SCLK_SPI0 15973#define CLK_SCLK_SPI1 16074#define CLK_SCLK_SPI2 16175#define CLK_SCLK_SLIMBUS 16276#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */77#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */78#define CLK_SCLK_PCM1 16579#define CLK_SCLK_PCM2 16680#define CLK_SCLK_I2S1 16781#define CLK_SCLK_I2S2 16882#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */83#define CLK_SCLK_MFC 17084#define CLK_SCLK_PCM0 17185#define CLK_SCLK_G3D 17286#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */87#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */88#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */89#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */90#define CLK_SCLK_FIMG2D 17791 92/* gate clocks */93#define CLK_SSS 25594#define CLK_FIMC0 25695#define CLK_FIMC1 25796#define CLK_FIMC2 25897#define CLK_FIMC3 25998#define CLK_CSIS0 26099#define CLK_CSIS1 261100#define CLK_JPEG 262101#define CLK_SMMU_FIMC0 263102#define CLK_SMMU_FIMC1 264103#define CLK_SMMU_FIMC2 265104#define CLK_SMMU_FIMC3 266105#define CLK_SMMU_JPEG 267106#define CLK_VP 268107#define CLK_MIXER 269108#define CLK_TVENC 270 /* Exynos4210 only */109#define CLK_HDMI 271110#define CLK_SMMU_TV 272111#define CLK_MFC 273112#define CLK_SMMU_MFCL 274113#define CLK_SMMU_MFCR 275114#define CLK_G3D 276115#define CLK_G2D 277116#define CLK_ROTATOR 278117#define CLK_MDMA 279118#define CLK_SMMU_G2D 280119#define CLK_SMMU_ROTATOR 281120#define CLK_SMMU_MDMA 282121#define CLK_FIMD0 283122#define CLK_MIE0 284123#define CLK_MDNIE0 285 /* Exynos4412 only */124#define CLK_DSIM0 286125#define CLK_SMMU_FIMD0 287126#define CLK_FIMD1 288 /* Exynos4210 only */127#define CLK_MIE1 289 /* Exynos4210 only */128#define CLK_DSIM1 290 /* Exynos4210 only */129#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */130#define CLK_PDMA0 292131#define CLK_PDMA1 293132#define CLK_PCIE_PHY 294133#define CLK_SATA_PHY 295 /* Exynos4210 only */134#define CLK_TSI 296135#define CLK_SDMMC0 297136#define CLK_SDMMC1 298137#define CLK_SDMMC2 299138#define CLK_SDMMC3 300139#define CLK_SDMMC4 301140#define CLK_SATA 302 /* Exynos4210 only */141#define CLK_SROMC 303142#define CLK_USB_HOST 304143#define CLK_USB_DEVICE 305144#define CLK_PCIE 306145#define CLK_ONENAND 307146#define CLK_NFCON 308147#define CLK_SMMU_PCIE 309148#define CLK_GPS 310149#define CLK_SMMU_GPS 311150#define CLK_UART0 312151#define CLK_UART1 313152#define CLK_UART2 314153#define CLK_UART3 315154#define CLK_UART4 316155#define CLK_I2C0 317156#define CLK_I2C1 318157#define CLK_I2C2 319158#define CLK_I2C3 320159#define CLK_I2C4 321160#define CLK_I2C5 322161#define CLK_I2C6 323162#define CLK_I2C7 324163#define CLK_I2C_HDMI 325164#define CLK_TSADC 326165#define CLK_SPI0 327166#define CLK_SPI1 328167#define CLK_SPI2 329168#define CLK_I2S1 330169#define CLK_I2S2 331170#define CLK_PCM0 332171#define CLK_I2S0 333172#define CLK_PCM1 334173#define CLK_PCM2 335174#define CLK_PWM 336175#define CLK_SLIMBUS 337176#define CLK_SPDIF 338177#define CLK_AC97 339178#define CLK_MODEMIF 340179#define CLK_CHIPID 341180#define CLK_SYSREG 342181#define CLK_HDMI_CEC 343182#define CLK_MCT 344183#define CLK_WDT 345184#define CLK_RTC 346185#define CLK_KEYIF 347186#define CLK_AUDSS 348187#define CLK_MIPI_HSI 349 /* Exynos4210 only */188#define CLK_PIXELASYNCM0 351189#define CLK_PIXELASYNCM1 352190#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */191#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */192#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */193#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */194#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */195#define CLK_TMU_APBIF 383196 197/* mux clocks */198#define CLK_MOUT_FIMC0 384199#define CLK_MOUT_FIMC1 385200#define CLK_MOUT_FIMC2 386201#define CLK_MOUT_FIMC3 387202#define CLK_MOUT_CAM0 388203#define CLK_MOUT_CAM1 389204#define CLK_MOUT_CSIS0 390205#define CLK_MOUT_CSIS1 391206#define CLK_MOUT_G3D0 392207#define CLK_MOUT_G3D1 393208#define CLK_MOUT_G3D 394209#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */210#define CLK_MOUT_HDMI 396211#define CLK_MOUT_MIXER 397212#define CLK_MOUT_VPLLSRC 398213 214/* gate clocks - ppmu */215#define CLK_PPMULEFT 400216#define CLK_PPMURIGHT 401217#define CLK_PPMUCAMIF 402218#define CLK_PPMUTV 403219#define CLK_PPMUMFC_L 404220#define CLK_PPMUMFC_R 405221#define CLK_PPMUG3D 406222#define CLK_PPMUIMAGE 407223#define CLK_PPMULCD0 408224#define CLK_PPMULCD1 409 /* Exynos4210 only */225#define CLK_PPMUFILE 410226#define CLK_PPMUGPS 411227#define CLK_PPMUDMC0 412228#define CLK_PPMUDMC1 413229#define CLK_PPMUCPU 414230#define CLK_PPMUACP 415231 232/* div clocks */233#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */234#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */235#define CLK_DIV_ACP 456236#define CLK_DIV_DMC 457237#define CLK_DIV_C2C 458 /* Exynos4x12 only */238#define CLK_DIV_GDL 459239#define CLK_DIV_GDR 460240#define CLK_DIV_CORE2 461241 242/* Exynos4x12 ISP clocks */243#define CLK_ISP_FIMC_ISP 1244#define CLK_ISP_FIMC_DRC 2245#define CLK_ISP_FIMC_FD 3246#define CLK_ISP_FIMC_LITE0 4247#define CLK_ISP_FIMC_LITE1 5248#define CLK_ISP_MCUISP 6249#define CLK_ISP_GICISP 7250#define CLK_ISP_SMMU_ISP 8251#define CLK_ISP_SMMU_DRC 9252#define CLK_ISP_SMMU_FD 10253#define CLK_ISP_SMMU_LITE0 11254#define CLK_ISP_SMMU_LITE1 12255#define CLK_ISP_PPMUISPMX 13256#define CLK_ISP_PPMUISPX 14257#define CLK_ISP_MCUCTL_ISP 15258#define CLK_ISP_MPWM_ISP 16259#define CLK_ISP_I2C0_ISP 17260#define CLK_ISP_I2C1_ISP 18261#define CLK_ISP_MTCADC_ISP 19262#define CLK_ISP_PWM_ISP 20263#define CLK_ISP_WDT_ISP 21264#define CLK_ISP_UART_ISP 22265#define CLK_ISP_ASYNCAXIM 23266#define CLK_ISP_SMMU_ISPCX 24267#define CLK_ISP_SPI0_ISP 25268#define CLK_ISP_SPI1_ISP 26269 270#define CLK_ISP_DIV_ISP0 27271#define CLK_ISP_DIV_ISP1 28272#define CLK_ISP_DIV_MCUISP0 29273#define CLK_ISP_DIV_MCUISP1 30274 275#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */276