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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.4 * Author: Andrzej Hajda <a.hajda@samsung.com>5 *6 * Device Tree binding constants for Exynos5250 clock controller.7 */8 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H10#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H11 12/* core clocks */13#define CLK_FIN_PLL 114#define CLK_FOUT_APLL 215#define CLK_FOUT_MPLL 316#define CLK_FOUT_BPLL 417#define CLK_FOUT_GPLL 518#define CLK_FOUT_CPLL 619#define CLK_FOUT_EPLL 720#define CLK_FOUT_VPLL 821#define CLK_ARM_CLK 922#define CLK_DIV_ARM2 1023 24/* gate for special clocks (sclk) */25#define CLK_SCLK_CAM_BAYER 12826#define CLK_SCLK_CAM0 12927#define CLK_SCLK_CAM1 13028#define CLK_SCLK_GSCL_WA 13129#define CLK_SCLK_GSCL_WB 13230#define CLK_SCLK_FIMD1 13331#define CLK_SCLK_MIPI1 13432#define CLK_SCLK_DP 13533#define CLK_SCLK_HDMI 13634#define CLK_SCLK_PIXEL 13735#define CLK_SCLK_AUDIO0 13836#define CLK_SCLK_MMC0 13937#define CLK_SCLK_MMC1 14038#define CLK_SCLK_MMC2 14139#define CLK_SCLK_MMC3 14240#define CLK_SCLK_SATA 14341#define CLK_SCLK_USB3 14442#define CLK_SCLK_JPEG 14543#define CLK_SCLK_UART0 14644#define CLK_SCLK_UART1 14745#define CLK_SCLK_UART2 14846#define CLK_SCLK_UART3 14947#define CLK_SCLK_PWM 15048#define CLK_SCLK_AUDIO1 15149#define CLK_SCLK_AUDIO2 15250#define CLK_SCLK_SPDIF 15351#define CLK_SCLK_SPI0 15452#define CLK_SCLK_SPI1 15553#define CLK_SCLK_SPI2 15654#define CLK_DIV_I2S1 15755#define CLK_DIV_I2S2 15856#define CLK_SCLK_HDMIPHY 15957#define CLK_DIV_PCM0 16058 59/* gate clocks */60#define CLK_GSCL0 25661#define CLK_GSCL1 25762#define CLK_GSCL2 25863#define CLK_GSCL3 25964#define CLK_GSCL_WA 26065#define CLK_GSCL_WB 26166#define CLK_SMMU_GSCL0 26267#define CLK_SMMU_GSCL1 26368#define CLK_SMMU_GSCL2 26469#define CLK_SMMU_GSCL3 26570#define CLK_MFC 26671#define CLK_SMMU_MFCL 26772#define CLK_SMMU_MFCR 26873#define CLK_ROTATOR 26974#define CLK_JPEG 27075#define CLK_MDMA1 27176#define CLK_SMMU_ROTATOR 27277#define CLK_SMMU_JPEG 27378#define CLK_SMMU_MDMA1 27479#define CLK_PDMA0 27580#define CLK_PDMA1 27681#define CLK_SATA 27782#define CLK_USBOTG 27883#define CLK_MIPI_HSI 27984#define CLK_SDMMC0 28085#define CLK_SDMMC1 28186#define CLK_SDMMC2 28287#define CLK_SDMMC3 28388#define CLK_SROMC 28489#define CLK_USB2 28590#define CLK_USB3 28691#define CLK_SATA_PHYCTRL 28792#define CLK_SATA_PHYI2C 28893#define CLK_UART0 28994#define CLK_UART1 29095#define CLK_UART2 29196#define CLK_UART3 29297#define CLK_UART4 29398#define CLK_I2C0 29499#define CLK_I2C1 295100#define CLK_I2C2 296101#define CLK_I2C3 297102#define CLK_I2C4 298103#define CLK_I2C5 299104#define CLK_I2C6 300105#define CLK_I2C7 301106#define CLK_I2C_HDMI 302107#define CLK_ADC 303108#define CLK_SPI0 304109#define CLK_SPI1 305110#define CLK_SPI2 306111#define CLK_I2S1 307112#define CLK_I2S2 308113#define CLK_PCM1 309114#define CLK_PCM2 310115#define CLK_PWM 311116#define CLK_SPDIF 312117#define CLK_AC97 313118#define CLK_HSI2C0 314119#define CLK_HSI2C1 315120#define CLK_HSI2C2 316121#define CLK_HSI2C3 317122#define CLK_CHIPID 318123#define CLK_SYSREG 319124#define CLK_PMU 320125#define CLK_CMU_TOP 321126#define CLK_CMU_CORE 322127#define CLK_CMU_MEM 323128#define CLK_TZPC0 324129#define CLK_TZPC1 325130#define CLK_TZPC2 326131#define CLK_TZPC3 327132#define CLK_TZPC4 328133#define CLK_TZPC5 329134#define CLK_TZPC6 330135#define CLK_TZPC7 331136#define CLK_TZPC8 332137#define CLK_TZPC9 333138#define CLK_HDMI_CEC 334139#define CLK_MCT 335140#define CLK_WDT 336141#define CLK_RTC 337142#define CLK_TMU 338143#define CLK_FIMD1 339144#define CLK_MIE1 340145#define CLK_DSIM0 341146#define CLK_DP 342147#define CLK_MIXER 343148#define CLK_HDMI 344149#define CLK_G2D 345150#define CLK_MDMA0 346151#define CLK_SMMU_MDMA0 347152#define CLK_SSS 348153#define CLK_G3D 349154#define CLK_SMMU_TV 350155#define CLK_SMMU_FIMD1 351156#define CLK_SMMU_2D 352157#define CLK_SMMU_FIMC_ISP 353158#define CLK_SMMU_FIMC_DRC 354159#define CLK_SMMU_FIMC_SCC 355160#define CLK_SMMU_FIMC_SCP 356161#define CLK_SMMU_FIMC_FD 357162#define CLK_SMMU_FIMC_MCU 358163#define CLK_SMMU_FIMC_ODC 359164#define CLK_SMMU_FIMC_DIS0 360165#define CLK_SMMU_FIMC_DIS1 361166#define CLK_SMMU_FIMC_3DNR 362167#define CLK_SMMU_FIMC_LITE0 363168#define CLK_SMMU_FIMC_LITE1 364169#define CLK_CAMIF_TOP 365170 171/* mux clocks */172#define CLK_MOUT_HDMI 1024173#define CLK_MOUT_GPLL 1025174#define CLK_MOUT_ACLK200_DISP1_SUB 1026175#define CLK_MOUT_ACLK300_DISP1_SUB 1027176#define CLK_MOUT_APLL 1028177#define CLK_MOUT_MPLL 1029178#define CLK_MOUT_VPLLSRC 1030179 180#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */181