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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.4 * Author: Rahul Sharma <rahul.sharma@samsung.com>5 *6 * Provides Constants for Exynos5260 clocks.7 */8 9#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H10#define _DT_BINDINGS_CLK_EXYNOS5260_H11 12/* Clock names: <cmu><type><IP> */13 14/* List Of Clocks For CMU_TOP */15 16#define TOP_FOUT_DISP_PLL 117#define TOP_FOUT_AUD_PLL 218#define TOP_MOUT_AUDTOP_PLL_USER 319#define TOP_MOUT_AUD_PLL 420#define TOP_MOUT_DISP_PLL 521#define TOP_MOUT_BUSTOP_PLL_USER 622#define TOP_MOUT_MEMTOP_PLL_USER 723#define TOP_MOUT_MEDIATOP_PLL_USER 824#define TOP_MOUT_DISP_DISP_333 925#define TOP_MOUT_ACLK_DISP_333 1026#define TOP_MOUT_DISP_DISP_222 1127#define TOP_MOUT_ACLK_DISP_222 1228#define TOP_MOUT_DISP_MEDIA_PIXEL 1329#define TOP_MOUT_FIMD1 1430#define TOP_MOUT_SCLK_PERI_SPI0_CLK 1531#define TOP_MOUT_SCLK_PERI_SPI1_CLK 1632#define TOP_MOUT_SCLK_PERI_SPI2_CLK 1733#define TOP_MOUT_SCLK_PERI_UART0_UCLK 1834#define TOP_MOUT_SCLK_PERI_UART2_UCLK 1935#define TOP_MOUT_SCLK_PERI_UART1_UCLK 2036#define TOP_MOUT_BUS4_BUSTOP_100 2137#define TOP_MOUT_BUS4_BUSTOP_400 2238#define TOP_MOUT_BUS3_BUSTOP_100 2339#define TOP_MOUT_BUS3_BUSTOP_400 2440#define TOP_MOUT_BUS2_BUSTOP_400 2541#define TOP_MOUT_BUS2_BUSTOP_100 2642#define TOP_MOUT_BUS1_BUSTOP_100 2743#define TOP_MOUT_BUS1_BUSTOP_400 2844#define TOP_MOUT_SCLK_FSYS_USB 2945#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 3046#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 3147#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 3248#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 3349#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 3450#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 3551#define TOP_MOUT_ACLK_ISP1_266 3652#define TOP_MOUT_ISP1_MEDIA_266 3753#define TOP_MOUT_ACLK_ISP1_400 3854#define TOP_MOUT_ISP1_MEDIA_400 3955#define TOP_MOUT_SCLK_ISP1_SPI0 4056#define TOP_MOUT_SCLK_ISP1_SPI1 4157#define TOP_MOUT_SCLK_ISP1_UART 4258#define TOP_MOUT_SCLK_ISP1_SENSOR2 4359#define TOP_MOUT_SCLK_ISP1_SENSOR1 4460#define TOP_MOUT_SCLK_ISP1_SENSOR0 4561#define TOP_MOUT_ACLK_MFC_333 4662#define TOP_MOUT_MFC_BUSTOP_333 4763#define TOP_MOUT_ACLK_G2D_333 4864#define TOP_MOUT_G2D_BUSTOP_333 4965#define TOP_MOUT_ACLK_GSCL_FIMC 5066#define TOP_MOUT_GSCL_BUSTOP_FIMC 5167#define TOP_MOUT_ACLK_GSCL_333 5268#define TOP_MOUT_GSCL_BUSTOP_333 5369#define TOP_MOUT_ACLK_GSCL_400 5470#define TOP_MOUT_M2M_MEDIATOP_400 5571#define TOP_DOUT_ACLK_MFC_333 5672#define TOP_DOUT_ACLK_G2D_333 5773#define TOP_DOUT_SCLK_ISP1_SENSOR2_A 5874#define TOP_DOUT_SCLK_ISP1_SENSOR1_A 5975#define TOP_DOUT_SCLK_ISP1_SENSOR0_A 6076#define TOP_DOUT_ACLK_GSCL_FIMC 6177#define TOP_DOUT_ACLK_GSCL_400 6278#define TOP_DOUT_ACLK_GSCL_333 6379#define TOP_DOUT_SCLK_ISP1_SPI0_B 6480#define TOP_DOUT_SCLK_ISP1_SPI0_A 6581#define TOP_DOUT_ACLK_ISP1_400 6682#define TOP_DOUT_ACLK_ISP1_266 6783#define TOP_DOUT_SCLK_ISP1_UART 6884#define TOP_DOUT_SCLK_ISP1_SPI1_B 6985#define TOP_DOUT_SCLK_ISP1_SPI1_A 7086#define TOP_DOUT_SCLK_ISP1_SENSOR2_B 7187#define TOP_DOUT_SCLK_ISP1_SENSOR1_B 7288#define TOP_DOUT_SCLK_ISP1_SENSOR0_B 7389#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 7490#define TOP_DOUT_SCLK_DISP_PIXEL 7591#define TOP_DOUT_ACLK_DISP_222 7692#define TOP_DOUT_ACLK_DISP_333 7793#define TOP_DOUT_ACLK_BUS4_100 7894#define TOP_DOUT_ACLK_BUS4_400 7995#define TOP_DOUT_ACLK_BUS3_100 8096#define TOP_DOUT_ACLK_BUS3_400 8197#define TOP_DOUT_ACLK_BUS2_100 8298#define TOP_DOUT_ACLK_BUS2_400 8399#define TOP_DOUT_ACLK_BUS1_100 84100#define TOP_DOUT_ACLK_BUS1_400 85101#define TOP_DOUT_SCLK_PERI_SPI1_B 86102#define TOP_DOUT_SCLK_PERI_SPI1_A 87103#define TOP_DOUT_SCLK_PERI_SPI0_B 88104#define TOP_DOUT_SCLK_PERI_SPI0_A 89105#define TOP_DOUT_SCLK_PERI_UART0 90106#define TOP_DOUT_SCLK_PERI_UART2 91107#define TOP_DOUT_SCLK_PERI_UART1 92108#define TOP_DOUT_SCLK_PERI_SPI2_B 93109#define TOP_DOUT_SCLK_PERI_SPI2_A 94110#define TOP_DOUT_ACLK_PERI_AUD 95111#define TOP_DOUT_ACLK_PERI_66 96112#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97113#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98114#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99115#define TOP_DOUT_ACLK_FSYS_200 100116#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101117#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102118#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103119#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104120#define TOP_SCLK_FIMD1 105121#define TOP_SCLK_MMC2 106122#define TOP_SCLK_MMC1 107123#define TOP_SCLK_MMC0 108124#define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109125#define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110126#define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111127#define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112128#define phyclk_hdmi_phy_tmds_clko 113129#define PHYCLK_HDMI_PHY_PIXEL_CLKO 114130#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115131#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116132#define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117133#define PHYCLK_DPTX_PHY_CLK_DIV2 118134#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119135#define PHYCLK_USBHOST20_PHY_PHYCLOCK 120136#define PHYCLK_USBHOST20_PHY_FREECLK 121137#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122138#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123139#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124140 141/* List Of Clocks For CMU_EGL */142 143#define EGL_FOUT_EGL_PLL 1144#define EGL_FOUT_EGL_DPLL 2145#define EGL_MOUT_EGL_B 3146#define EGL_MOUT_EGL_PLL 4147#define EGL_DOUT_EGL_PLL 5148#define EGL_DOUT_EGL_PCLK_DBG 6149#define EGL_DOUT_EGL_ATCLK 7150#define EGL_DOUT_PCLK_EGL 8151#define EGL_DOUT_ACLK_EGL 9152#define EGL_DOUT_EGL2 10153#define EGL_DOUT_EGL1 11154 155/* List Of Clocks For CMU_KFC */156 157#define KFC_FOUT_KFC_PLL 1158#define KFC_MOUT_KFC_PLL 2159#define KFC_MOUT_KFC 3160#define KFC_DOUT_KFC_PLL 4161#define KFC_DOUT_PCLK_KFC 5162#define KFC_DOUT_ACLK_KFC 6163#define KFC_DOUT_KFC_PCLK_DBG 7164#define KFC_DOUT_KFC_ATCLK 8165#define KFC_DOUT_KFC2 9166#define KFC_DOUT_KFC1 10167 168/* List Of Clocks For CMU_MIF */169 170#define MIF_FOUT_MEM_PLL 1171#define MIF_FOUT_MEDIA_PLL 2172#define MIF_FOUT_BUS_PLL 3173#define MIF_MOUT_CLK2X_PHY 4174#define MIF_MOUT_MIF_DREX2X 5175#define MIF_MOUT_CLKM_PHY 6176#define MIF_MOUT_MIF_DREX 7177#define MIF_MOUT_MEDIA_PLL 8178#define MIF_MOUT_BUS_PLL 9179#define MIF_MOUT_MEM_PLL 10180#define MIF_DOUT_ACLK_BUS_100 11181#define MIF_DOUT_ACLK_BUS_200 12182#define MIF_DOUT_ACLK_MIF_466 13183#define MIF_DOUT_CLK2X_PHY 14184#define MIF_DOUT_CLKM_PHY 15185#define MIF_DOUT_BUS_PLL 16186#define MIF_DOUT_MEM_PLL 17187#define MIF_DOUT_MEDIA_PLL 18188#define MIF_CLK_LPDDR3PHY_WRAP1 19189#define MIF_CLK_LPDDR3PHY_WRAP0 20190#define MIF_CLK_MONOCNT 21191#define MIF_CLK_MIF_RTC 22192#define MIF_CLK_DREX1 23193#define MIF_CLK_DREX0 24194#define MIF_CLK_INTMEM 25195#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26196#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27197 198/* List Of Clocks For CMU_G3D */199 200#define G3D_FOUT_G3D_PLL 1201#define G3D_MOUT_G3D_PLL 2202#define G3D_DOUT_PCLK_G3D 3203#define G3D_DOUT_ACLK_G3D 4204#define G3D_CLK_G3D_HPM 5205#define G3D_CLK_G3D 6206 207/* List Of Clocks For CMU_AUD */208 209#define AUD_MOUT_SCLK_AUD_PCM 1210#define AUD_MOUT_SCLK_AUD_I2S 2211#define AUD_MOUT_AUD_PLL_USER 3212#define AUD_DOUT_ACLK_AUD_131 4213#define AUD_DOUT_SCLK_AUD_UART 5214#define AUD_DOUT_SCLK_AUD_PCM 6215#define AUD_DOUT_SCLK_AUD_I2S 7216#define AUD_CLK_AUD_UART 8217#define AUD_CLK_PCM 9218#define AUD_CLK_I2S 10219#define AUD_CLK_DMAC 11220#define AUD_CLK_SRAMC 12221#define AUD_SCLK_AUD_UART 13222#define AUD_SCLK_PCM 14223#define AUD_SCLK_I2S 15224 225/* List Of Clocks For CMU_MFC */226 227#define MFC_MOUT_ACLK_MFC_333_USER 1228#define MFC_DOUT_PCLK_MFC_83 2229#define MFC_CLK_MFC 3230#define MFC_CLK_SMMU2_MFCM1 4231#define MFC_CLK_SMMU2_MFCM0 5232 233/* List Of Clocks For CMU_GSCL */234 235#define GSCL_MOUT_ACLK_CSIS 1236#define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2237#define GSCL_MOUT_ACLK_M2M_400_USER 3238#define GSCL_MOUT_ACLK_GSCL_333_USER 4239#define GSCL_DOUT_ACLK_CSIS_200 5240#define GSCL_DOUT_PCLK_M2M_100 6241#define GSCL_CLK_PIXEL_GSCL1 7242#define GSCL_CLK_PIXEL_GSCL0 8243#define GSCL_CLK_MSCL1 9244#define GSCL_CLK_MSCL0 10245#define GSCL_CLK_GSCL1 11246#define GSCL_CLK_GSCL0 12247#define GSCL_CLK_FIMC_LITE_D 13248#define GSCL_CLK_FIMC_LITE_B 14249#define GSCL_CLK_FIMC_LITE_A 15250#define GSCL_CLK_CSIS1 16251#define GSCL_CLK_CSIS0 17252#define GSCL_CLK_SMMU3_LITE_D 18253#define GSCL_CLK_SMMU3_LITE_B 19254#define GSCL_CLK_SMMU3_LITE_A 20255#define GSCL_CLK_SMMU3_GSCL0 21256#define GSCL_CLK_SMMU3_GSCL1 22257#define GSCL_CLK_SMMU3_MSCL0 23258#define GSCL_CLK_SMMU3_MSCL1 24259#define GSCL_SCLK_CSIS1_WRAP 25260#define GSCL_SCLK_CSIS0_WRAP 26261 262/* List Of Clocks For CMU_FSYS */263 264#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1265#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2266#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3267#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4268#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5269#define FSYS_CLK_TSI 6270#define FSYS_CLK_USBLINK 7271#define FSYS_CLK_USBHOST20 8272#define FSYS_CLK_USBDRD30 9273#define FSYS_CLK_SROMC 10274#define FSYS_CLK_PDMA 11275#define FSYS_CLK_MMC2 12276#define FSYS_CLK_MMC1 13277#define FSYS_CLK_MMC0 14278#define FSYS_CLK_RTIC 15279#define FSYS_CLK_SMMU_RTIC 16280#define FSYS_PHYCLK_USBDRD30 17281#define FSYS_PHYCLK_USBHOST20 18282 283/* List Of Clocks For CMU_PERI */284 285#define PERI_MOUT_SCLK_SPDIF 1286#define PERI_MOUT_SCLK_I2SCOD 2287#define PERI_MOUT_SCLK_PCM 3288#define PERI_DOUT_I2S 4289#define PERI_DOUT_PCM 5290#define PERI_CLK_WDT_KFC 6291#define PERI_CLK_WDT_EGL 7292#define PERI_CLK_HSIC3 8293#define PERI_CLK_HSIC2 9294#define PERI_CLK_HSIC1 10295#define PERI_CLK_HSIC0 11296#define PERI_CLK_PCM 12297#define PERI_CLK_MCT 13298#define PERI_CLK_I2S 14299#define PERI_CLK_I2CHDMI 15300#define PERI_CLK_I2C7 16301#define PERI_CLK_I2C6 17302#define PERI_CLK_I2C5 18303#define PERI_CLK_I2C4 19304#define PERI_CLK_I2C9 20305#define PERI_CLK_I2C8 21306#define PERI_CLK_I2C11 22307#define PERI_CLK_I2C10 23308#define PERI_CLK_HDMICEC 24309#define PERI_CLK_EFUSE_WRITER 25310#define PERI_CLK_ABB 26311#define PERI_CLK_UART2 27312#define PERI_CLK_UART1 28313#define PERI_CLK_UART0 29314#define PERI_CLK_ADC 30315#define PERI_CLK_TMU4 31316#define PERI_CLK_TMU3 32317#define PERI_CLK_TMU2 33318#define PERI_CLK_TMU1 34319#define PERI_CLK_TMU0 35320#define PERI_CLK_SPI2 36321#define PERI_CLK_SPI1 37322#define PERI_CLK_SPI0 38323#define PERI_CLK_SPDIF 39324#define PERI_CLK_PWM 40325#define PERI_CLK_UART4 41326#define PERI_CLK_CHIPID 42327#define PERI_CLK_PROVKEY0 43328#define PERI_CLK_PROVKEY1 44329#define PERI_CLK_SECKEY 45330#define PERI_CLK_TOP_RTC 46331#define PERI_CLK_TZPC10 47332#define PERI_CLK_TZPC9 48333#define PERI_CLK_TZPC8 49334#define PERI_CLK_TZPC7 50335#define PERI_CLK_TZPC6 51336#define PERI_CLK_TZPC5 52337#define PERI_CLK_TZPC4 53338#define PERI_CLK_TZPC3 54339#define PERI_CLK_TZPC2 55340#define PERI_CLK_TZPC1 56341#define PERI_CLK_TZPC0 57342#define PERI_SCLK_UART2 58343#define PERI_SCLK_UART1 59344#define PERI_SCLK_UART0 60345#define PERI_SCLK_SPI2 61346#define PERI_SCLK_SPI1 62347#define PERI_SCLK_SPI0 63348#define PERI_SCLK_SPDIF 64349#define PERI_SCLK_I2S 65350#define PERI_SCLK_PCM1 66351 352/* List Of Clocks For CMU_DISP */353 354#define DISP_MOUT_SCLK_HDMI_SPDIF 1355#define DISP_MOUT_SCLK_HDMI_PIXEL 2356#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3357#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4358#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5359#define DISP_MOUT_HDMI_PHY_PIXEL 6360#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7361#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8362#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9363#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10364#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11365#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12366#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13367#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14368#define DISP_MOUT_ACLK_DISP_222_USER 15369#define DISP_MOUT_SCLK_DISP_PIXEL_USER 16370#define DISP_MOUT_ACLK_DISP_333_USER 17371#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18372#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19373#define DISP_DOUT_PCLK_DISP_111 20374#define DISP_CLK_SMMU_TV 21375#define DISP_CLK_SMMU_FIMD1M1 22376#define DISP_CLK_SMMU_FIMD1M0 23377#define DISP_CLK_PIXEL_MIXER 24378#define DISP_CLK_PIXEL_DISP 25379#define DISP_CLK_MIXER 26380#define DISP_CLK_MIPIPHY 27381#define DISP_CLK_HDMIPHY 28382#define DISP_CLK_HDMI 29383#define DISP_CLK_FIMD1 30384#define DISP_CLK_DSIM1 31385#define DISP_CLK_DPPHY 32386#define DISP_CLK_DP 33387#define DISP_SCLK_PIXEL 34388#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35389 390/* List Of Clocks For CMU_G2D */391 392#define G2D_MOUT_ACLK_G2D_333_USER 1393#define G2D_DOUT_PCLK_G2D_83 2394#define G2D_CLK_SMMU3_JPEG 3395#define G2D_CLK_MDMA 4396#define G2D_CLK_JPEG 5397#define G2D_CLK_G2D 6398#define G2D_CLK_SSS 7399#define G2D_CLK_SLIM_SSS 8400#define G2D_CLK_SMMU_SLIM_SSS 9401#define G2D_CLK_SMMU_SSS 10402#define G2D_CLK_SMMU_MDMA 11403#define G2D_CLK_SMMU3_G2D 12404 405/* List Of Clocks For CMU_ISP */406 407#define ISP_MOUT_ISP_400_USER 1408#define ISP_MOUT_ISP_266_USER 2409#define ISP_DOUT_SCLK_MPWM 3410#define ISP_DOUT_CA5_PCLKDBG 4411#define ISP_DOUT_CA5_ATCLKIN 5412#define ISP_DOUT_PCLK_ISP_133 6413#define ISP_DOUT_PCLK_ISP_66 7414#define ISP_CLK_GIC 8415#define ISP_CLK_WDT 9416#define ISP_CLK_UART 10417#define ISP_CLK_SPI1 11418#define ISP_CLK_SPI0 12419#define ISP_CLK_SMMU_SCALERP 13420#define ISP_CLK_SMMU_SCALERC 14421#define ISP_CLK_SMMU_ISPCX 15422#define ISP_CLK_SMMU_ISP 16423#define ISP_CLK_SMMU_FD 17424#define ISP_CLK_SMMU_DRC 18425#define ISP_CLK_PWM 19426#define ISP_CLK_MTCADC 20427#define ISP_CLK_MPWM 21428#define ISP_CLK_MCUCTL 22429#define ISP_CLK_I2C1 23430#define ISP_CLK_I2C0 24431#define ISP_CLK_FIMC_SCALERP 25432#define ISP_CLK_FIMC_SCALERC 26433#define ISP_CLK_FIMC 27434#define ISP_CLK_FIMC_FD 28435#define ISP_CLK_FIMC_DRC 29436#define ISP_CLK_CA5 30437#define ISP_SCLK_SPI0_EXT 31438#define ISP_SCLK_SPI1_EXT 32439#define ISP_SCLK_UART_EXT 33440 441#endif442