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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.4 * Copyright (c) 2016 Krzysztof Kozlowski5 *6 * Device Tree binding constants for Exynos5421 clock controller.7 */8 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H10#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H11 12/* core clocks */13#define CLK_FIN_PLL 114#define CLK_FOUT_APLL 215#define CLK_FOUT_CPLL 316#define CLK_FOUT_MPLL 417#define CLK_FOUT_BPLL 518#define CLK_FOUT_KPLL 619#define CLK_FOUT_EPLL 720 21/* gate for special clocks (sclk) */22#define CLK_SCLK_UART0 12823#define CLK_SCLK_UART1 12924#define CLK_SCLK_UART2 13025#define CLK_SCLK_UART3 13126#define CLK_SCLK_MMC0 13227#define CLK_SCLK_MMC1 13328#define CLK_SCLK_MMC2 13429#define CLK_SCLK_USBD300 15030#define CLK_SCLK_USBD301 15131#define CLK_SCLK_USBPHY300 15232#define CLK_SCLK_USBPHY301 15333#define CLK_SCLK_PWM 15534 35/* gate clocks */36#define CLK_UART0 25737#define CLK_UART1 25838#define CLK_UART2 25939#define CLK_UART3 26040#define CLK_I2C0 26141#define CLK_I2C1 26242#define CLK_I2C2 26343#define CLK_I2C3 26444#define CLK_USI0 26545#define CLK_USI1 26646#define CLK_USI2 26747#define CLK_USI3 26848#define CLK_TSADC 27049#define CLK_PWM 27950#define CLK_MCT 31551#define CLK_WDT 31652#define CLK_RTC 31753#define CLK_TMU 31854#define CLK_MMC0 35155#define CLK_MMC1 35256#define CLK_MMC2 35357#define CLK_PDMA0 36258#define CLK_PDMA1 36359#define CLK_USBH20 36560#define CLK_USBD300 36661#define CLK_USBD301 36762#define CLK_SSS 47163 64#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */65