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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.4 * Author: Andrzej Hajda <a.hajda@samsung.com>5 *6 * Device Tree binding constants for Exynos5420 clock controller.7 */8 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H10#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H11 12/* core clocks */13#define CLK_FIN_PLL 114#define CLK_FOUT_APLL 215#define CLK_FOUT_CPLL 316#define CLK_FOUT_DPLL 417#define CLK_FOUT_EPLL 518#define CLK_FOUT_RPLL 619#define CLK_FOUT_IPLL 720#define CLK_FOUT_SPLL 821#define CLK_FOUT_VPLL 922#define CLK_FOUT_MPLL 1023#define CLK_FOUT_BPLL 1124#define CLK_FOUT_KPLL 1225#define CLK_ARM_CLK 1326#define CLK_KFC_CLK 1427 28/* gate for special clocks (sclk) */29#define CLK_SCLK_UART0 12830#define CLK_SCLK_UART1 12931#define CLK_SCLK_UART2 13032#define CLK_SCLK_UART3 13133#define CLK_SCLK_MMC0 13234#define CLK_SCLK_MMC1 13335#define CLK_SCLK_MMC2 13436#define CLK_SCLK_SPI0 13537#define CLK_SCLK_SPI1 13638#define CLK_SCLK_SPI2 13739#define CLK_SCLK_I2S1 13840#define CLK_SCLK_I2S2 13941#define CLK_SCLK_PCM1 14042#define CLK_SCLK_PCM2 14143#define CLK_SCLK_SPDIF 14244#define CLK_SCLK_HDMI 14345#define CLK_SCLK_PIXEL 14446#define CLK_SCLK_DP1 14547#define CLK_SCLK_MIPI1 14648#define CLK_SCLK_FIMD1 14749#define CLK_SCLK_MAUDIO0 14850#define CLK_SCLK_MAUPCM0 14951#define CLK_SCLK_USBD300 15052#define CLK_SCLK_USBD301 15153#define CLK_SCLK_USBPHY300 15254#define CLK_SCLK_USBPHY301 15355#define CLK_SCLK_UNIPRO 15456#define CLK_SCLK_PWM 15557#define CLK_SCLK_GSCL_WA 15658#define CLK_SCLK_GSCL_WB 15759#define CLK_SCLK_HDMIPHY 15860#define CLK_MAU_EPLL 15961#define CLK_SCLK_HSIC_12M 16062#define CLK_SCLK_MPHY_IXTAL24 16163#define CLK_SCLK_BPLL 16264 65/* gate clocks */66#define CLK_UART0 25767#define CLK_UART1 25868#define CLK_UART2 25969#define CLK_UART3 26070#define CLK_I2C0 26171#define CLK_I2C1 26272#define CLK_I2C2 26373#define CLK_I2C3 26474#define CLK_USI0 26575#define CLK_USI1 26676#define CLK_USI2 26777#define CLK_USI3 26878#define CLK_I2C_HDMI 26979#define CLK_TSADC 27080#define CLK_SPI0 27181#define CLK_SPI1 27282#define CLK_SPI2 27383#define CLK_KEYIF 27484#define CLK_I2S1 27585#define CLK_I2S2 27686#define CLK_PCM1 27787#define CLK_PCM2 27888#define CLK_PWM 27989#define CLK_SPDIF 28090#define CLK_USI4 28191#define CLK_USI5 28292#define CLK_USI6 28393#define CLK_ACLK66_PSGEN 30094#define CLK_CHIPID 30195#define CLK_SYSREG 30296#define CLK_TZPC0 30397#define CLK_TZPC1 30498#define CLK_TZPC2 30599#define CLK_TZPC3 306100#define CLK_TZPC4 307101#define CLK_TZPC5 308102#define CLK_TZPC6 309103#define CLK_TZPC7 310104#define CLK_TZPC8 311105#define CLK_TZPC9 312106#define CLK_HDMI_CEC 313107#define CLK_SECKEY 314108#define CLK_MCT 315109#define CLK_WDT 316110#define CLK_RTC 317111#define CLK_TMU 318112#define CLK_TMU_GPU 319113#define CLK_PCLK66_GPIO 330114#define CLK_ACLK200_FSYS2 350115#define CLK_MMC0 351116#define CLK_MMC1 352117#define CLK_MMC2 353118#define CLK_SROMC 354119#define CLK_UFS 355120#define CLK_ACLK200_FSYS 360121#define CLK_TSI 361122#define CLK_PDMA0 362123#define CLK_PDMA1 363124#define CLK_RTIC 364125#define CLK_USBH20 365126#define CLK_USBD300 366127#define CLK_USBD301 367128#define CLK_ACLK400_MSCL 380129#define CLK_MSCL0 381130#define CLK_MSCL1 382131#define CLK_MSCL2 383132#define CLK_SMMU_MSCL0 384133#define CLK_SMMU_MSCL1 385134#define CLK_SMMU_MSCL2 386135#define CLK_ACLK333 400136#define CLK_MFC 401137#define CLK_SMMU_MFCL 402138#define CLK_SMMU_MFCR 403139#define CLK_ACLK200_DISP1 410140#define CLK_DSIM1 411141#define CLK_DP1 412142#define CLK_HDMI 413143#define CLK_ACLK300_DISP1 420144#define CLK_FIMD1 421145#define CLK_SMMU_FIMD1M0 422146#define CLK_SMMU_FIMD1M1 423147#define CLK_ACLK166 430148#define CLK_MIXER 431149#define CLK_ACLK266 440150#define CLK_ROTATOR 441151#define CLK_MDMA1 442152#define CLK_SMMU_ROTATOR 443153#define CLK_SMMU_MDMA1 444154#define CLK_ACLK300_JPEG 450155#define CLK_JPEG 451156#define CLK_JPEG2 452157#define CLK_SMMU_JPEG 453158#define CLK_SMMU_JPEG2 454159#define CLK_ACLK300_GSCL 460160#define CLK_SMMU_GSCL0 461161#define CLK_SMMU_GSCL1 462162#define CLK_GSCL_WA 463163#define CLK_GSCL_WB 464164#define CLK_GSCL0 465165#define CLK_GSCL1 466166#define CLK_FIMC_3AA 467167#define CLK_ACLK266_G2D 470168#define CLK_SSS 471169#define CLK_SLIM_SSS 472170#define CLK_MDMA0 473171#define CLK_ACLK333_G2D 480172#define CLK_G2D 481173#define CLK_ACLK333_432_GSCL 490174#define CLK_SMMU_3AA 491175#define CLK_SMMU_FIMCL0 492176#define CLK_SMMU_FIMCL1 493177#define CLK_SMMU_FIMCL3 494178#define CLK_FIMC_LITE3 495179#define CLK_FIMC_LITE0 496180#define CLK_FIMC_LITE1 497181#define CLK_ACLK_G3D 500182#define CLK_G3D 501183#define CLK_SMMU_MIXER 502184#define CLK_SMMU_G2D 503185#define CLK_SMMU_MDMA0 504186#define CLK_MC 505187#define CLK_TOP_RTC 506188#define CLK_SCLK_UART_ISP 510189#define CLK_SCLK_SPI0_ISP 511190#define CLK_SCLK_SPI1_ISP 512191#define CLK_SCLK_PWM_ISP 513192#define CLK_SCLK_ISP_SENSOR0 514193#define CLK_SCLK_ISP_SENSOR1 515194#define CLK_SCLK_ISP_SENSOR2 516195#define CLK_ACLK432_SCALER 517196#define CLK_ACLK432_CAM 518197#define CLK_ACLK_FL1550_CAM 519198#define CLK_ACLK550_CAM 520199#define CLK_CLKM_PHY0 521200#define CLK_CLKM_PHY1 522201#define CLK_ACLK_PPMU_DREX0_0 523202#define CLK_ACLK_PPMU_DREX0_1 524203#define CLK_ACLK_PPMU_DREX1_0 525204#define CLK_ACLK_PPMU_DREX1_1 526205#define CLK_PCLK_PPMU_DREX0_0 527206#define CLK_PCLK_PPMU_DREX0_1 528207#define CLK_PCLK_PPMU_DREX1_0 529208#define CLK_PCLK_PPMU_DREX1_1 530209 210/* mux clocks */211#define CLK_MOUT_HDMI 640212#define CLK_MOUT_G3D 641213#define CLK_MOUT_VPLL 642214#define CLK_MOUT_MAUDIO0 643215#define CLK_MOUT_USER_ACLK333 644216#define CLK_MOUT_SW_ACLK333 645217#define CLK_MOUT_USER_ACLK200_DISP1 646218#define CLK_MOUT_SW_ACLK200 647219#define CLK_MOUT_USER_ACLK300_DISP1 648220#define CLK_MOUT_SW_ACLK300 649221#define CLK_MOUT_USER_ACLK400_DISP1 650222#define CLK_MOUT_SW_ACLK400 651223#define CLK_MOUT_USER_ACLK300_GSCL 652224#define CLK_MOUT_SW_ACLK300_GSCL 653225#define CLK_MOUT_MCLK_CDREX 654226#define CLK_MOUT_BPLL 655227#define CLK_MOUT_MX_MSPLL_CCORE 656228#define CLK_MOUT_EPLL 657229#define CLK_MOUT_MAU_EPLL 658230#define CLK_MOUT_USER_MAU_EPLL 659231#define CLK_MOUT_SCLK_SPLL 660232#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661233#define CLK_MOUT_SW_ACLK_G3D 662234#define CLK_MOUT_APLL 663235#define CLK_MOUT_MSPLL_CPU 664236#define CLK_MOUT_KPLL 665237#define CLK_MOUT_MSPLL_KFC 666238 239 240/* divider clocks */241#define CLK_DOUT_PIXEL 768242#define CLK_DOUT_ACLK400_WCORE 769243#define CLK_DOUT_ACLK400_ISP 770244#define CLK_DOUT_ACLK400_MSCL 771245#define CLK_DOUT_ACLK200 772246#define CLK_DOUT_ACLK200_FSYS2 773247#define CLK_DOUT_ACLK100_NOC 774248#define CLK_DOUT_PCLK200_FSYS 775249#define CLK_DOUT_ACLK200_FSYS 776250#define CLK_DOUT_ACLK333_432_GSCL 777251#define CLK_DOUT_ACLK333_432_ISP 778252#define CLK_DOUT_ACLK66 779253#define CLK_DOUT_ACLK333_432_ISP0 780254#define CLK_DOUT_ACLK266 781255#define CLK_DOUT_ACLK166 782256#define CLK_DOUT_ACLK333 783257#define CLK_DOUT_ACLK333_G2D 784258#define CLK_DOUT_ACLK266_G2D 785259#define CLK_DOUT_ACLK_G3D 786260#define CLK_DOUT_ACLK300_JPEG 787261#define CLK_DOUT_ACLK300_DISP1 788262#define CLK_DOUT_ACLK300_GSCL 789263#define CLK_DOUT_ACLK400_DISP1 790264#define CLK_DOUT_PCLK_CDREX 791265#define CLK_DOUT_SCLK_CDREX 792266#define CLK_DOUT_ACLK_CDREX1 793267#define CLK_DOUT_CCLK_DREX0 794268#define CLK_DOUT_CLK2X_PHY0 795269#define CLK_DOUT_PCLK_CORE_MEM 796270#define CLK_FF_DOUT_SPLL2 797271#define CLK_DOUT_PCLK_DREX0 798272#define CLK_DOUT_PCLK_DREX1 799273 274#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */275