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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.4 * Author: Chanwoo Choi <cw00.choi@samsung.com>5 */6 7#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H8#define _DT_BINDINGS_CLOCK_EXYNOS5433_H9 10/* CMU_TOP */11#define CLK_FOUT_ISP_PLL 112#define CLK_FOUT_AUD_PLL 213 14#define CLK_MOUT_AUD_PLL 1015#define CLK_MOUT_ISP_PLL 1116#define CLK_MOUT_AUD_PLL_USER_T 1217#define CLK_MOUT_MPHY_PLL_USER 1318#define CLK_MOUT_MFC_PLL_USER 1419#define CLK_MOUT_BUS_PLL_USER 1520#define CLK_MOUT_ACLK_HEVC_400 1621#define CLK_MOUT_ACLK_CAM1_333 1722#define CLK_MOUT_ACLK_CAM1_552_B 1823#define CLK_MOUT_ACLK_CAM1_552_A 1924#define CLK_MOUT_ACLK_ISP_DIS_400 2025#define CLK_MOUT_ACLK_ISP_400 2126#define CLK_MOUT_ACLK_BUS0_400 2227#define CLK_MOUT_ACLK_MSCL_400_B 2328#define CLK_MOUT_ACLK_MSCL_400_A 2429#define CLK_MOUT_ACLK_GSCL_333 2530#define CLK_MOUT_ACLK_G2D_400_B 2631#define CLK_MOUT_ACLK_G2D_400_A 2732#define CLK_MOUT_SCLK_JPEG_C 2833#define CLK_MOUT_SCLK_JPEG_B 2934#define CLK_MOUT_SCLK_JPEG_A 3035#define CLK_MOUT_SCLK_MMC2_B 3136#define CLK_MOUT_SCLK_MMC2_A 3237#define CLK_MOUT_SCLK_MMC1_B 3338#define CLK_MOUT_SCLK_MMC1_A 3439#define CLK_MOUT_SCLK_MMC0_D 3540#define CLK_MOUT_SCLK_MMC0_C 3641#define CLK_MOUT_SCLK_MMC0_B 3742#define CLK_MOUT_SCLK_MMC0_A 3843#define CLK_MOUT_SCLK_SPI4 3944#define CLK_MOUT_SCLK_SPI3 4045#define CLK_MOUT_SCLK_UART2 4146#define CLK_MOUT_SCLK_UART1 4247#define CLK_MOUT_SCLK_UART0 4348#define CLK_MOUT_SCLK_SPI2 4449#define CLK_MOUT_SCLK_SPI1 4550#define CLK_MOUT_SCLK_SPI0 4651#define CLK_MOUT_ACLK_MFC_400_C 4752#define CLK_MOUT_ACLK_MFC_400_B 4853#define CLK_MOUT_ACLK_MFC_400_A 4954#define CLK_MOUT_SCLK_ISP_SENSOR2 5055#define CLK_MOUT_SCLK_ISP_SENSOR1 5156#define CLK_MOUT_SCLK_ISP_SENSOR0 5257#define CLK_MOUT_SCLK_ISP_UART 5358#define CLK_MOUT_SCLK_ISP_SPI1 5459#define CLK_MOUT_SCLK_ISP_SPI0 5560#define CLK_MOUT_SCLK_PCIE_100 5661#define CLK_MOUT_SCLK_UFSUNIPRO 5762#define CLK_MOUT_SCLK_USBHOST30 5863#define CLK_MOUT_SCLK_USBDRD30 5964#define CLK_MOUT_SCLK_SLIMBUS 6065#define CLK_MOUT_SCLK_SPDIF 6166#define CLK_MOUT_SCLK_AUDIO1 6267#define CLK_MOUT_SCLK_AUDIO0 6368#define CLK_MOUT_SCLK_HDMI_SPDIF 6469 70#define CLK_DIV_ACLK_FSYS_200 10071#define CLK_DIV_ACLK_IMEM_SSSX_266 10172#define CLK_DIV_ACLK_IMEM_200 10273#define CLK_DIV_ACLK_IMEM_266 10374#define CLK_DIV_ACLK_PERIC_66_B 10475#define CLK_DIV_ACLK_PERIC_66_A 10576#define CLK_DIV_ACLK_PERIS_66_B 10677#define CLK_DIV_ACLK_PERIS_66_A 10778#define CLK_DIV_SCLK_MMC1_B 10879#define CLK_DIV_SCLK_MMC1_A 10980#define CLK_DIV_SCLK_MMC0_B 11081#define CLK_DIV_SCLK_MMC0_A 11182#define CLK_DIV_SCLK_MMC2_B 11283#define CLK_DIV_SCLK_MMC2_A 11384#define CLK_DIV_SCLK_SPI1_B 11485#define CLK_DIV_SCLK_SPI1_A 11586#define CLK_DIV_SCLK_SPI0_B 11687#define CLK_DIV_SCLK_SPI0_A 11788#define CLK_DIV_SCLK_SPI2_B 11889#define CLK_DIV_SCLK_SPI2_A 11990#define CLK_DIV_SCLK_UART2 12091#define CLK_DIV_SCLK_UART1 12192#define CLK_DIV_SCLK_UART0 12293#define CLK_DIV_SCLK_SPI4_B 12394#define CLK_DIV_SCLK_SPI4_A 12495#define CLK_DIV_SCLK_SPI3_B 12596#define CLK_DIV_SCLK_SPI3_A 12697#define CLK_DIV_SCLK_I2S1 12798#define CLK_DIV_SCLK_PCM1 12899#define CLK_DIV_SCLK_AUDIO1 129100#define CLK_DIV_SCLK_AUDIO0 130101#define CLK_DIV_ACLK_GSCL_111 131102#define CLK_DIV_ACLK_GSCL_333 132103#define CLK_DIV_ACLK_HEVC_400 133104#define CLK_DIV_ACLK_MFC_400 134105#define CLK_DIV_ACLK_G2D_266 135106#define CLK_DIV_ACLK_G2D_400 136107#define CLK_DIV_ACLK_G3D_400 137108#define CLK_DIV_ACLK_BUS0_400 138109#define CLK_DIV_ACLK_BUS1_400 139110#define CLK_DIV_SCLK_PCIE_100 140111#define CLK_DIV_SCLK_USBHOST30 141112#define CLK_DIV_SCLK_UFSUNIPRO 142113#define CLK_DIV_SCLK_USBDRD30 143114#define CLK_DIV_SCLK_JPEG 144115#define CLK_DIV_ACLK_MSCL_400 145116#define CLK_DIV_ACLK_ISP_DIS_400 146117#define CLK_DIV_ACLK_ISP_400 147118#define CLK_DIV_ACLK_CAM0_333 148119#define CLK_DIV_ACLK_CAM0_400 149120#define CLK_DIV_ACLK_CAM0_552 150121#define CLK_DIV_ACLK_CAM1_333 151122#define CLK_DIV_ACLK_CAM1_400 152123#define CLK_DIV_ACLK_CAM1_552 153124#define CLK_DIV_SCLK_ISP_UART 154125#define CLK_DIV_SCLK_ISP_SPI1_B 155126#define CLK_DIV_SCLK_ISP_SPI1_A 156127#define CLK_DIV_SCLK_ISP_SPI0_B 157128#define CLK_DIV_SCLK_ISP_SPI0_A 158129#define CLK_DIV_SCLK_ISP_SENSOR2_B 159130#define CLK_DIV_SCLK_ISP_SENSOR2_A 160131#define CLK_DIV_SCLK_ISP_SENSOR1_B 161132#define CLK_DIV_SCLK_ISP_SENSOR1_A 162133#define CLK_DIV_SCLK_ISP_SENSOR0_B 163134#define CLK_DIV_SCLK_ISP_SENSOR0_A 164135 136#define CLK_ACLK_PERIC_66 200137#define CLK_ACLK_PERIS_66 201138#define CLK_ACLK_FSYS_200 202139#define CLK_SCLK_MMC2_FSYS 203140#define CLK_SCLK_MMC1_FSYS 204141#define CLK_SCLK_MMC0_FSYS 205142#define CLK_SCLK_SPI4_PERIC 206143#define CLK_SCLK_SPI3_PERIC 207144#define CLK_SCLK_UART2_PERIC 208145#define CLK_SCLK_UART1_PERIC 209146#define CLK_SCLK_UART0_PERIC 210147#define CLK_SCLK_SPI2_PERIC 211148#define CLK_SCLK_SPI1_PERIC 212149#define CLK_SCLK_SPI0_PERIC 213150#define CLK_SCLK_SPDIF_PERIC 214151#define CLK_SCLK_I2S1_PERIC 215152#define CLK_SCLK_PCM1_PERIC 216153#define CLK_SCLK_SLIMBUS 217154#define CLK_SCLK_AUDIO1 218155#define CLK_SCLK_AUDIO0 219156#define CLK_ACLK_G2D_266 220157#define CLK_ACLK_G2D_400 221158#define CLK_ACLK_G3D_400 222159#define CLK_ACLK_IMEM_SSSX_266 223160#define CLK_ACLK_BUS0_400 224161#define CLK_ACLK_BUS1_400 225162#define CLK_ACLK_IMEM_200 226163#define CLK_ACLK_IMEM_266 227164#define CLK_SCLK_PCIE_100_FSYS 228165#define CLK_SCLK_UFSUNIPRO_FSYS 229166#define CLK_SCLK_USBHOST30_FSYS 230167#define CLK_SCLK_USBDRD30_FSYS 231168#define CLK_ACLK_GSCL_111 232169#define CLK_ACLK_GSCL_333 233170#define CLK_SCLK_JPEG_MSCL 234171#define CLK_ACLK_MSCL_400 235172#define CLK_ACLK_MFC_400 236173#define CLK_ACLK_HEVC_400 237174#define CLK_ACLK_ISP_DIS_400 238175#define CLK_ACLK_ISP_400 239176#define CLK_ACLK_CAM0_333 240177#define CLK_ACLK_CAM0_400 241178#define CLK_ACLK_CAM0_552 242179#define CLK_ACLK_CAM1_333 243180#define CLK_ACLK_CAM1_400 244181#define CLK_ACLK_CAM1_552 245182#define CLK_SCLK_ISP_SENSOR2 246183#define CLK_SCLK_ISP_SENSOR1 247184#define CLK_SCLK_ISP_SENSOR0 248185#define CLK_SCLK_ISP_MCTADC_CAM1 249186#define CLK_SCLK_ISP_UART_CAM1 250187#define CLK_SCLK_ISP_SPI1_CAM1 251188#define CLK_SCLK_ISP_SPI0_CAM1 252189#define CLK_SCLK_HDMI_SPDIF_DISP 253190 191/* CMU_CPIF */192#define CLK_FOUT_MPHY_PLL 1193 194#define CLK_MOUT_MPHY_PLL 2195 196#define CLK_DIV_SCLK_MPHY 10197 198#define CLK_SCLK_MPHY_PLL 11199#define CLK_SCLK_UFS_MPHY 11200 201/* CMU_MIF */202#define CLK_FOUT_MEM0_PLL 1203#define CLK_FOUT_MEM1_PLL 2204#define CLK_FOUT_BUS_PLL 3205#define CLK_FOUT_MFC_PLL 4206#define CLK_DOUT_MFC_PLL 5207#define CLK_DOUT_BUS_PLL 6208#define CLK_DOUT_MEM1_PLL 7209#define CLK_DOUT_MEM0_PLL 8210 211#define CLK_MOUT_MFC_PLL_DIV2 10212#define CLK_MOUT_BUS_PLL_DIV2 11213#define CLK_MOUT_MEM1_PLL_DIV2 12214#define CLK_MOUT_MEM0_PLL_DIV2 13215#define CLK_MOUT_MFC_PLL 14216#define CLK_MOUT_BUS_PLL 15217#define CLK_MOUT_MEM1_PLL 16218#define CLK_MOUT_MEM0_PLL 17219#define CLK_MOUT_CLK2X_PHY_C 18220#define CLK_MOUT_CLK2X_PHY_B 19221#define CLK_MOUT_CLK2X_PHY_A 20222#define CLK_MOUT_CLKM_PHY_C 21223#define CLK_MOUT_CLKM_PHY_B 22224#define CLK_MOUT_CLKM_PHY_A 23225#define CLK_MOUT_ACLK_MIFNM_200 24226#define CLK_MOUT_ACLK_MIFNM_400 25227#define CLK_MOUT_ACLK_DISP_333_B 26228#define CLK_MOUT_ACLK_DISP_333_A 27229#define CLK_MOUT_SCLK_DECON_VCLK_C 28230#define CLK_MOUT_SCLK_DECON_VCLK_B 29231#define CLK_MOUT_SCLK_DECON_VCLK_A 30232#define CLK_MOUT_SCLK_DECON_ECLK_C 31233#define CLK_MOUT_SCLK_DECON_ECLK_B 32234#define CLK_MOUT_SCLK_DECON_ECLK_A 33235#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34236#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35237#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36238#define CLK_MOUT_SCLK_DSD_C 37239#define CLK_MOUT_SCLK_DSD_B 38240#define CLK_MOUT_SCLK_DSD_A 39241#define CLK_MOUT_SCLK_DSIM0_C 40242#define CLK_MOUT_SCLK_DSIM0_B 41243#define CLK_MOUT_SCLK_DSIM0_A 42244#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46245#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47246#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48247#define CLK_MOUT_SCLK_DSIM1_C 49248#define CLK_MOUT_SCLK_DSIM1_B 50249#define CLK_MOUT_SCLK_DSIM1_A 51250 251#define CLK_DIV_SCLK_HPM_MIF 55252#define CLK_DIV_ACLK_DREX1 56253#define CLK_DIV_ACLK_DREX0 57254#define CLK_DIV_CLK2XPHY 58255#define CLK_DIV_ACLK_MIF_266 59256#define CLK_DIV_ACLK_MIFND_133 60257#define CLK_DIV_ACLK_MIF_133 61258#define CLK_DIV_ACLK_MIFNM_200 62259#define CLK_DIV_ACLK_MIF_200 63260#define CLK_DIV_ACLK_MIF_400 64261#define CLK_DIV_ACLK_BUS2_400 65262#define CLK_DIV_ACLK_DISP_333 66263#define CLK_DIV_ACLK_CPIF_200 67264#define CLK_DIV_SCLK_DSIM1 68265#define CLK_DIV_SCLK_DECON_TV_VCLK 69266#define CLK_DIV_SCLK_DSIM0 70267#define CLK_DIV_SCLK_DSD 71268#define CLK_DIV_SCLK_DECON_TV_ECLK 72269#define CLK_DIV_SCLK_DECON_VCLK 73270#define CLK_DIV_SCLK_DECON_ECLK 74271#define CLK_DIV_MIF_PRE 75272 273#define CLK_CLK2X_PHY1 80274#define CLK_CLK2X_PHY0 81275#define CLK_CLKM_PHY1 82276#define CLK_CLKM_PHY0 83277#define CLK_RCLK_DREX1 84278#define CLK_RCLK_DREX0 85279#define CLK_ACLK_DREX1_TZ 86280#define CLK_ACLK_DREX0_TZ 87281#define CLK_ACLK_DREX1_PEREV 88282#define CLK_ACLK_DREX0_PEREV 89283#define CLK_ACLK_DREX1_MEMIF 90284#define CLK_ACLK_DREX0_MEMIF 91285#define CLK_ACLK_DREX1_SCH 92286#define CLK_ACLK_DREX0_SCH 93287#define CLK_ACLK_DREX1_BUSIF 94288#define CLK_ACLK_DREX0_BUSIF 95289#define CLK_ACLK_DREX1_BUSIF_RD 96290#define CLK_ACLK_DREX0_BUSIF_RD 97291#define CLK_ACLK_DREX1 98292#define CLK_ACLK_DREX0 99293#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100294#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101295#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102296#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103297#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104298#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105299#define CLK_ACLK_ASYNCAXIS_CP1 106300#define CLK_ACLK_ASYNCAXIM_CP1 107301#define CLK_ACLK_ASYNCAXIS_CP0 108302#define CLK_ACLK_ASYNCAXIM_CP0 109303#define CLK_ACLK_ASYNCAXIS_DREX1_3 110304#define CLK_ACLK_ASYNCAXIM_DREX1_3 111305#define CLK_ACLK_ASYNCAXIS_DREX1_1 112306#define CLK_ACLK_ASYNCAXIM_DREX1_1 113307#define CLK_ACLK_ASYNCAXIS_DREX1_0 114308#define CLK_ACLK_ASYNCAXIM_DREX1_0 115309#define CLK_ACLK_ASYNCAXIS_DREX0_3 116310#define CLK_ACLK_ASYNCAXIM_DREX0_3 117311#define CLK_ACLK_ASYNCAXIS_DREX0_1 118312#define CLK_ACLK_ASYNCAXIM_DREX0_1 119313#define CLK_ACLK_ASYNCAXIS_DREX0_0 120314#define CLK_ACLK_ASYNCAXIM_DREX0_0 121315#define CLK_ACLK_AHB2APB_MIF2P 122316#define CLK_ACLK_AHB2APB_MIF1P 123317#define CLK_ACLK_AHB2APB_MIF0P 124318#define CLK_ACLK_IXIU_CCI 125319#define CLK_ACLK_XIU_MIFSFRX 126320#define CLK_ACLK_MIFNP_133 127321#define CLK_ACLK_MIFNM_200 128322#define CLK_ACLK_MIFND_133 129323#define CLK_ACLK_MIFND_400 130324#define CLK_ACLK_CCI 131325#define CLK_ACLK_MIFND_266 132326#define CLK_ACLK_PPMU_DREX1S3 133327#define CLK_ACLK_PPMU_DREX1S1 134328#define CLK_ACLK_PPMU_DREX1S0 135329#define CLK_ACLK_PPMU_DREX0S3 136330#define CLK_ACLK_PPMU_DREX0S1 137331#define CLK_ACLK_PPMU_DREX0S0 138332#define CLK_ACLK_BTS_APOLLO 139333#define CLK_ACLK_BTS_ATLAS 140334#define CLK_ACLK_ACE_SEL_APOLL 141335#define CLK_ACLK_ACE_SEL_ATLAS 142336#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143337#define CLK_ACLK_AXIUS_ATLAS_CCI 144338#define CLK_ACLK_AXISYNCDNS_CCI 145339#define CLK_ACLK_AXISYNCDN_CCI 146340#define CLK_ACLK_AXISYNCDN_NOC_D 147341#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148342#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149343#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150344#define CLK_ACLK_BUS2_400 151345#define CLK_ACLK_DISP_333 152346#define CLK_ACLK_CPIF_200 153347#define CLK_PCLK_PPMU_DREX1S3 154348#define CLK_PCLK_PPMU_DREX1S1 155349#define CLK_PCLK_PPMU_DREX1S0 156350#define CLK_PCLK_PPMU_DREX0S3 157351#define CLK_PCLK_PPMU_DREX0S1 158352#define CLK_PCLK_PPMU_DREX0S0 159353#define CLK_PCLK_BTS_APOLLO 160354#define CLK_PCLK_BTS_ATLAS 161355#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162356#define CLK_PCLK_ASYNCAXI_CP1 163357#define CLK_PCLK_ASYNCAXI_CP0 164358#define CLK_PCLK_ASYNCAXI_DREX1_3 165359#define CLK_PCLK_ASYNCAXI_DREX1_1 166360#define CLK_PCLK_ASYNCAXI_DREX1_0 167361#define CLK_PCLK_ASYNCAXI_DREX0_3 168362#define CLK_PCLK_ASYNCAXI_DREX0_1 169363#define CLK_PCLK_ASYNCAXI_DREX0_0 170364#define CLK_PCLK_MIFSRVND_133 171365#define CLK_PCLK_PMU_MIF 172366#define CLK_PCLK_SYSREG_MIF 173367#define CLK_PCLK_GPIO_ALIVE 174368#define CLK_PCLK_ABB 175369#define CLK_PCLK_PMU_APBIF 176370#define CLK_PCLK_DDR_PHY1 177371#define CLK_PCLK_DREX1 178372#define CLK_PCLK_DDR_PHY0 179373#define CLK_PCLK_DREX0 180374#define CLK_PCLK_DREX0_TZ 181375#define CLK_PCLK_DREX1_TZ 182376#define CLK_PCLK_MONOTONIC_CNT 183377#define CLK_PCLK_RTC 184378#define CLK_SCLK_DSIM1_DISP 185379#define CLK_SCLK_DECON_TV_VCLK_DISP 186380#define CLK_SCLK_FREQ_DET_BUS_PLL 187381#define CLK_SCLK_FREQ_DET_MFC_PLL 188382#define CLK_SCLK_FREQ_DET_MEM0_PLL 189383#define CLK_SCLK_FREQ_DET_MEM1_PLL 190384#define CLK_SCLK_DSIM0_DISP 191385#define CLK_SCLK_DSD_DISP 192386#define CLK_SCLK_DECON_TV_ECLK_DISP 193387#define CLK_SCLK_DECON_VCLK_DISP 194388#define CLK_SCLK_DECON_ECLK_DISP 195389#define CLK_SCLK_HPM_MIF 196390#define CLK_SCLK_MFC_PLL 197391#define CLK_SCLK_BUS_PLL 198392#define CLK_SCLK_BUS_PLL_APOLLO 199393#define CLK_SCLK_BUS_PLL_ATLAS 200394 395/* CMU_PERIC */396#define CLK_PCLK_SPI2 1397#define CLK_PCLK_SPI1 2398#define CLK_PCLK_SPI0 3399#define CLK_PCLK_UART2 4400#define CLK_PCLK_UART1 5401#define CLK_PCLK_UART0 6402#define CLK_PCLK_HSI2C3 7403#define CLK_PCLK_HSI2C2 8404#define CLK_PCLK_HSI2C1 9405#define CLK_PCLK_HSI2C0 10406#define CLK_PCLK_I2C7 11407#define CLK_PCLK_I2C6 12408#define CLK_PCLK_I2C5 13409#define CLK_PCLK_I2C4 14410#define CLK_PCLK_I2C3 15411#define CLK_PCLK_I2C2 16412#define CLK_PCLK_I2C1 17413#define CLK_PCLK_I2C0 18414#define CLK_PCLK_SPI4 19415#define CLK_PCLK_SPI3 20416#define CLK_PCLK_HSI2C11 21417#define CLK_PCLK_HSI2C10 22418#define CLK_PCLK_HSI2C9 23419#define CLK_PCLK_HSI2C8 24420#define CLK_PCLK_HSI2C7 25421#define CLK_PCLK_HSI2C6 26422#define CLK_PCLK_HSI2C5 27423#define CLK_PCLK_HSI2C4 28424#define CLK_SCLK_SPI4 29425#define CLK_SCLK_SPI3 30426#define CLK_SCLK_SPI2 31427#define CLK_SCLK_SPI1 32428#define CLK_SCLK_SPI0 33429#define CLK_SCLK_UART2 34430#define CLK_SCLK_UART1 35431#define CLK_SCLK_UART0 36432#define CLK_ACLK_AHB2APB_PERIC2P 37433#define CLK_ACLK_AHB2APB_PERIC1P 38434#define CLK_ACLK_AHB2APB_PERIC0P 39435#define CLK_ACLK_PERICNP_66 40436#define CLK_PCLK_SCI 41437#define CLK_PCLK_GPIO_FINGER 42438#define CLK_PCLK_GPIO_ESE 43439#define CLK_PCLK_PWM 44440#define CLK_PCLK_SPDIF 45441#define CLK_PCLK_PCM1 46442#define CLK_PCLK_I2S1 47443#define CLK_PCLK_ADCIF 48444#define CLK_PCLK_GPIO_TOUCH 49445#define CLK_PCLK_GPIO_NFC 50446#define CLK_PCLK_GPIO_PERIC 51447#define CLK_PCLK_PMU_PERIC 52448#define CLK_PCLK_SYSREG_PERIC 53449#define CLK_SCLK_IOCLK_SPI4 54450#define CLK_SCLK_IOCLK_SPI3 55451#define CLK_SCLK_SCI 56452#define CLK_SCLK_SC_IN 57453#define CLK_SCLK_PWM 58454#define CLK_SCLK_IOCLK_SPI2 59455#define CLK_SCLK_IOCLK_SPI1 60456#define CLK_SCLK_IOCLK_SPI0 61457#define CLK_SCLK_IOCLK_I2S1_BCLK 62458#define CLK_SCLK_SPDIF 63459#define CLK_SCLK_PCM1 64460#define CLK_SCLK_I2S1 65461 462#define CLK_DIV_SCLK_SCI 70463#define CLK_DIV_SCLK_SC_IN 71464 465/* CMU_PERIS */466#define CLK_PCLK_HPM_APBIF 1467#define CLK_PCLK_TMU1_APBIF 2468#define CLK_PCLK_TMU0_APBIF 3469#define CLK_PCLK_PMU_PERIS 4470#define CLK_PCLK_SYSREG_PERIS 5471#define CLK_PCLK_CMU_TOP_APBIF 6472#define CLK_PCLK_WDT_APOLLO 7473#define CLK_PCLK_WDT_ATLAS 8474#define CLK_PCLK_MCT 9475#define CLK_PCLK_HDMI_CEC 10476#define CLK_ACLK_AHB2APB_PERIS1P 11477#define CLK_ACLK_AHB2APB_PERIS0P 12478#define CLK_ACLK_PERISNP_66 13479#define CLK_PCLK_TZPC12 14480#define CLK_PCLK_TZPC11 15481#define CLK_PCLK_TZPC10 16482#define CLK_PCLK_TZPC9 17483#define CLK_PCLK_TZPC8 18484#define CLK_PCLK_TZPC7 19485#define CLK_PCLK_TZPC6 20486#define CLK_PCLK_TZPC5 21487#define CLK_PCLK_TZPC4 22488#define CLK_PCLK_TZPC3 23489#define CLK_PCLK_TZPC2 24490#define CLK_PCLK_TZPC1 25491#define CLK_PCLK_TZPC0 26492#define CLK_PCLK_SECKEY_APBIF 27493#define CLK_PCLK_CHIPID_APBIF 28494#define CLK_PCLK_TOPRTC 29495#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30496#define CLK_PCLK_ANTIRBK_CNT_APBIF 31497#define CLK_PCLK_OTP_CON_APBIF 32498#define CLK_SCLK_ASV_TB 33499#define CLK_SCLK_TMU1 34500#define CLK_SCLK_TMU0 35501#define CLK_SCLK_SECKEY 36502#define CLK_SCLK_CHIPID 37503#define CLK_SCLK_TOPRTC 38504#define CLK_SCLK_CUSTOM_EFUSE 39505#define CLK_SCLK_ANTIRBK_CNT 40506#define CLK_SCLK_OTP_CON 41507 508/* CMU_FSYS */509#define CLK_MOUT_ACLK_FSYS_200_USER 1510#define CLK_MOUT_SCLK_MMC2_USER 2511#define CLK_MOUT_SCLK_MMC1_USER 3512#define CLK_MOUT_SCLK_MMC0_USER 4513#define CLK_MOUT_SCLK_UFS_MPHY_USER 5514#define CLK_MOUT_SCLK_PCIE_100_USER 6515#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7516#define CLK_MOUT_SCLK_USBHOST30_USER 8517#define CLK_MOUT_SCLK_USBDRD30_USER 9518#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10519#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11520#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12521#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13522#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14523#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15524#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16525#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17526#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18527#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19528#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20529#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21530#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22531#define CLK_MOUT_SCLK_MPHY 23532 533#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25534#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26535#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27536#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28537#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29538#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30539#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31540#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32541#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33542#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34543#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35544#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36545#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37546 547#define CLK_ACLK_PCIE 50548#define CLK_ACLK_PDMA1 51549#define CLK_ACLK_TSI 52550#define CLK_ACLK_MMC2 53551#define CLK_ACLK_MMC1 54552#define CLK_ACLK_MMC0 55553#define CLK_ACLK_UFS 56554#define CLK_ACLK_USBHOST20 57555#define CLK_ACLK_USBHOST30 58556#define CLK_ACLK_USBDRD30 59557#define CLK_ACLK_PDMA0 60558#define CLK_SCLK_MMC2 61559#define CLK_SCLK_MMC1 62560#define CLK_SCLK_MMC0 63561#define CLK_PDMA1 64562#define CLK_PDMA0 65563#define CLK_ACLK_XIU_FSYSPX 66564#define CLK_ACLK_AHB_USBLINKH1 67565#define CLK_ACLK_SMMU_PDMA1 68566#define CLK_ACLK_BTS_PCIE 69567#define CLK_ACLK_AXIUS_PDMA1 70568#define CLK_ACLK_SMMU_PDMA0 71569#define CLK_ACLK_BTS_UFS 72570#define CLK_ACLK_BTS_USBHOST30 73571#define CLK_ACLK_BTS_USBDRD30 74572#define CLK_ACLK_AXIUS_PDMA0 75573#define CLK_ACLK_AXIUS_USBHS 76574#define CLK_ACLK_AXIUS_FSYSSX 77575#define CLK_ACLK_AHB2APB_FSYSP 78576#define CLK_ACLK_AHB2AXI_USBHS 79577#define CLK_ACLK_AHB_USBLINKH0 80578#define CLK_ACLK_AHB_USBHS 81579#define CLK_ACLK_AHB_FSYSH 82580#define CLK_ACLK_XIU_FSYSX 83581#define CLK_ACLK_XIU_FSYSSX 84582#define CLK_ACLK_FSYSNP_200 85583#define CLK_ACLK_FSYSND_200 86584#define CLK_PCLK_PCIE_CTRL 87585#define CLK_PCLK_SMMU_PDMA1 88586#define CLK_PCLK_PCIE_PHY 89587#define CLK_PCLK_BTS_PCIE 90588#define CLK_PCLK_SMMU_PDMA0 91589#define CLK_PCLK_BTS_UFS 92590#define CLK_PCLK_BTS_USBHOST30 93591#define CLK_PCLK_BTS_USBDRD30 94592#define CLK_PCLK_GPIO_FSYS 95593#define CLK_PCLK_PMU_FSYS 96594#define CLK_PCLK_SYSREG_FSYS 97595#define CLK_SCLK_PCIE_100 98596#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99597#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100598#define CLK_PHYCLK_UFS_RX1_SYMBOL 101599#define CLK_PHYCLK_UFS_RX0_SYMBOL 102600#define CLK_PHYCLK_UFS_TX1_SYMBOL 103601#define CLK_PHYCLK_UFS_TX0_SYMBOL 104602#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105603#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106604#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107605#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108606#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109607#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110608#define CLK_SCLK_MPHY 111609#define CLK_SCLK_UFSUNIPRO 112610#define CLK_SCLK_USBHOST30 113611#define CLK_SCLK_USBDRD30 114612#define CLK_PCIE 115613 614/* CMU_G2D */615#define CLK_MUX_ACLK_G2D_266_USER 1616#define CLK_MUX_ACLK_G2D_400_USER 2617 618#define CLK_DIV_PCLK_G2D 3619 620#define CLK_ACLK_SMMU_MDMA1 4621#define CLK_ACLK_BTS_MDMA1 5622#define CLK_ACLK_BTS_G2D 6623#define CLK_ACLK_ALB_G2D 7624#define CLK_ACLK_AXIUS_G2DX 8625#define CLK_ACLK_ASYNCAXI_SYSX 9626#define CLK_ACLK_AHB2APB_G2D1P 10627#define CLK_ACLK_AHB2APB_G2D0P 11628#define CLK_ACLK_XIU_G2DX 12629#define CLK_ACLK_G2DNP_133 13630#define CLK_ACLK_G2DND_400 14631#define CLK_ACLK_MDMA1 15632#define CLK_ACLK_G2D 16633#define CLK_ACLK_SMMU_G2D 17634#define CLK_PCLK_SMMU_MDMA1 18635#define CLK_PCLK_BTS_MDMA1 19636#define CLK_PCLK_BTS_G2D 20637#define CLK_PCLK_ALB_G2D 21638#define CLK_PCLK_ASYNCAXI_SYSX 22639#define CLK_PCLK_PMU_G2D 23640#define CLK_PCLK_SYSREG_G2D 24641#define CLK_PCLK_G2D 25642#define CLK_PCLK_SMMU_G2D 26643 644/* CMU_DISP */645#define CLK_FOUT_DISP_PLL 1646 647#define CLK_MOUT_DISP_PLL 2648#define CLK_MOUT_SCLK_DSIM1_USER 3649#define CLK_MOUT_SCLK_DSIM0_USER 4650#define CLK_MOUT_SCLK_DSD_USER 5651#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6652#define CLK_MOUT_SCLK_DECON_VCLK_USER 7653#define CLK_MOUT_SCLK_DECON_ECLK_USER 8654#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9655#define CLK_MOUT_ACLK_DISP_333_USER 10656#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11657#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12658#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13659#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14660#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15661#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16662#define CLK_MOUT_SCLK_DSIM0 17663#define CLK_MOUT_SCLK_DECON_TV_ECLK 18664#define CLK_MOUT_SCLK_DECON_VCLK 19665#define CLK_MOUT_SCLK_DECON_ECLK 20666#define CLK_MOUT_SCLK_DSIM1_B_DISP 21667#define CLK_MOUT_SCLK_DSIM1_A_DISP 22668#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23669#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24670#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25671 672#define CLK_DIV_SCLK_DSIM1_DISP 30673#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31674#define CLK_DIV_SCLK_DSIM0_DISP 32675#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33676#define CLK_DIV_SCLK_DECON_VCLK_DISP 34677#define CLK_DIV_SCLK_DECON_ECLK_DISP 35678#define CLK_DIV_PCLK_DISP 36679 680#define CLK_ACLK_DECON_TV 40681#define CLK_ACLK_DECON 41682#define CLK_ACLK_SMMU_TV1X 42683#define CLK_ACLK_SMMU_TV0X 43684#define CLK_ACLK_SMMU_DECON1X 44685#define CLK_ACLK_SMMU_DECON0X 45686#define CLK_ACLK_BTS_DECON_TV_M3 46687#define CLK_ACLK_BTS_DECON_TV_M2 47688#define CLK_ACLK_BTS_DECON_TV_M1 48689#define CLK_ACLK_BTS_DECON_TV_M0 49690#define CLK_ACLK_BTS_DECON_NM4 50691#define CLK_ACLK_BTS_DECON_NM3 51692#define CLK_ACLK_BTS_DECON_NM2 52693#define CLK_ACLK_BTS_DECON_NM1 53694#define CLK_ACLK_BTS_DECON_NM0 54695#define CLK_ACLK_AHB2APB_DISPSFR2P 55696#define CLK_ACLK_AHB2APB_DISPSFR1P 56697#define CLK_ACLK_AHB2APB_DISPSFR0P 57698#define CLK_ACLK_AHB_DISPH 58699#define CLK_ACLK_XIU_TV1X 59700#define CLK_ACLK_XIU_TV0X 60701#define CLK_ACLK_XIU_DECON1X 61702#define CLK_ACLK_XIU_DECON0X 62703#define CLK_ACLK_XIU_DISP1X 63704#define CLK_ACLK_XIU_DISPNP_100 64705#define CLK_ACLK_DISP1ND_333 65706#define CLK_ACLK_DISP0ND_333 66707#define CLK_PCLK_SMMU_TV1X 67708#define CLK_PCLK_SMMU_TV0X 68709#define CLK_PCLK_SMMU_DECON1X 69710#define CLK_PCLK_SMMU_DECON0X 70711#define CLK_PCLK_BTS_DECON_TV_M3 71712#define CLK_PCLK_BTS_DECON_TV_M2 72713#define CLK_PCLK_BTS_DECON_TV_M1 73714#define CLK_PCLK_BTS_DECON_TV_M0 74715#define CLK_PCLK_BTS_DECONM4 75716#define CLK_PCLK_BTS_DECONM3 76717#define CLK_PCLK_BTS_DECONM2 77718#define CLK_PCLK_BTS_DECONM1 78719#define CLK_PCLK_BTS_DECONM0 79720#define CLK_PCLK_MIC1 80721#define CLK_PCLK_PMU_DISP 81722#define CLK_PCLK_SYSREG_DISP 82723#define CLK_PCLK_HDMIPHY 83724#define CLK_PCLK_HDMI 84725#define CLK_PCLK_MIC0 85726#define CLK_PCLK_DSIM1 86727#define CLK_PCLK_DSIM0 87728#define CLK_PCLK_DECON_TV 88729#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89730#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90731#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91732#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92733#define CLK_SCLK_DSIM1 93734#define CLK_SCLK_DECON_TV_VCLK 94735#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95736#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96737#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97738#define CLK_PHYCLK_HDMI_PIXEL 98739#define CLK_SCLK_RGB_VCLK_TO_SMIES 99740#define CLK_SCLK_FREQ_DET_DISP_PLL 100741#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101742#define CLK_SCLK_RGB_VCLK_TO_MIC0 102743#define CLK_SCLK_DSD 103744#define CLK_SCLK_HDMI_SPDIF 104745#define CLK_SCLK_DSIM0 105746#define CLK_SCLK_DECON_TV_ECLK 106747#define CLK_SCLK_DECON_VCLK 107748#define CLK_SCLK_DECON_ECLK 108749#define CLK_SCLK_RGB_VCLK 109750#define CLK_SCLK_RGB_TV_VCLK 110751 752#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111753#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112754 755#define CLK_PCLK_DECON 113756 757#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114758#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115759 760/* CMU_AUD */761#define CLK_MOUT_AUD_PLL_USER 1762#define CLK_MOUT_SCLK_AUD_PCM 2763#define CLK_MOUT_SCLK_AUD_I2S 3764 765#define CLK_DIV_ATCLK_AUD 4766#define CLK_DIV_PCLK_DBG_AUD 5767#define CLK_DIV_ACLK_AUD 6768#define CLK_DIV_AUD_CA5 7769#define CLK_DIV_SCLK_AUD_SLIMBUS 8770#define CLK_DIV_SCLK_AUD_UART 9771#define CLK_DIV_SCLK_AUD_PCM 10772#define CLK_DIV_SCLK_AUD_I2S 11773 774#define CLK_ACLK_INTR_CTRL 12775#define CLK_ACLK_AXIDS2_LPASSP 13776#define CLK_ACLK_AXIDS1_LPASSP 14777#define CLK_ACLK_AXI2APB1_LPASSP 15778#define CLK_ACLK_AXI2APH_LPASSP 16779#define CLK_ACLK_SMMU_LPASSX 17780#define CLK_ACLK_AXIDS0_LPASSP 18781#define CLK_ACLK_AXI2APB0_LPASSP 19782#define CLK_ACLK_XIU_LPASSX 20783#define CLK_ACLK_AUDNP_133 21784#define CLK_ACLK_AUDND_133 22785#define CLK_ACLK_SRAMC 23786#define CLK_ACLK_DMAC 24787#define CLK_PCLK_WDT1 25788#define CLK_PCLK_WDT0 26789#define CLK_PCLK_SFR1 27790#define CLK_PCLK_SMMU_LPASSX 28791#define CLK_PCLK_GPIO_AUD 29792#define CLK_PCLK_PMU_AUD 30793#define CLK_PCLK_SYSREG_AUD 31794#define CLK_PCLK_AUD_SLIMBUS 32795#define CLK_PCLK_AUD_UART 33796#define CLK_PCLK_AUD_PCM 34797#define CLK_PCLK_AUD_I2S 35798#define CLK_PCLK_TIMER 36799#define CLK_PCLK_SFR0_CTRL 37800#define CLK_ATCLK_AUD 38801#define CLK_PCLK_DBG_AUD 39802#define CLK_SCLK_AUD_CA5 40803#define CLK_SCLK_JTAG_TCK 41804#define CLK_SCLK_SLIMBUS_CLKIN 42805#define CLK_SCLK_AUD_SLIMBUS 43806#define CLK_SCLK_AUD_UART 44807#define CLK_SCLK_AUD_PCM 45808#define CLK_SCLK_I2S_BCLK 46809#define CLK_SCLK_AUD_I2S 47810 811/* CMU_BUS{0|1|2} */812#define CLK_DIV_PCLK_BUS_133 1813 814#define CLK_ACLK_AHB2APB_BUSP 2815#define CLK_ACLK_BUSNP_133 3816#define CLK_ACLK_BUSND_400 4817#define CLK_PCLK_BUSSRVND_133 5818#define CLK_PCLK_PMU_BUS 6819#define CLK_PCLK_SYSREG_BUS 7820 821#define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */822#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */823#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */824 825/* CMU_G3D */826#define CLK_FOUT_G3D_PLL 1827 828#define CLK_MOUT_ACLK_G3D_400 2829#define CLK_MOUT_G3D_PLL 3830 831#define CLK_DIV_SCLK_HPM_G3D 4832#define CLK_DIV_PCLK_G3D 5833#define CLK_DIV_ACLK_G3D 6834#define CLK_ACLK_BTS_G3D1 7835#define CLK_ACLK_BTS_G3D0 8836#define CLK_ACLK_ASYNCAPBS_G3D 9837#define CLK_ACLK_ASYNCAPBM_G3D 10838#define CLK_ACLK_AHB2APB_G3DP 11839#define CLK_ACLK_G3DNP_150 12840#define CLK_ACLK_G3DND_600 13841#define CLK_ACLK_G3D 14842#define CLK_PCLK_BTS_G3D1 15843#define CLK_PCLK_BTS_G3D0 16844#define CLK_PCLK_PMU_G3D 17845#define CLK_PCLK_SYSREG_G3D 18846#define CLK_SCLK_HPM_G3D 19847 848/* CMU_GSCL */849#define CLK_MOUT_ACLK_GSCL_111_USER 1850#define CLK_MOUT_ACLK_GSCL_333_USER 2851 852#define CLK_ACLK_BTS_GSCL2 3853#define CLK_ACLK_BTS_GSCL1 4854#define CLK_ACLK_BTS_GSCL0 5855#define CLK_ACLK_AHB2APB_GSCLP 6856#define CLK_ACLK_XIU_GSCLX 7857#define CLK_ACLK_GSCLNP_111 8858#define CLK_ACLK_GSCLRTND_333 9859#define CLK_ACLK_GSCLBEND_333 10860#define CLK_ACLK_GSD 11861#define CLK_ACLK_GSCL2 12862#define CLK_ACLK_GSCL1 13863#define CLK_ACLK_GSCL0 14864#define CLK_ACLK_SMMU_GSCL0 15865#define CLK_ACLK_SMMU_GSCL1 16866#define CLK_ACLK_SMMU_GSCL2 17867#define CLK_PCLK_BTS_GSCL2 18868#define CLK_PCLK_BTS_GSCL1 19869#define CLK_PCLK_BTS_GSCL0 20870#define CLK_PCLK_PMU_GSCL 21871#define CLK_PCLK_SYSREG_GSCL 22872#define CLK_PCLK_GSCL2 23873#define CLK_PCLK_GSCL1 24874#define CLK_PCLK_GSCL0 25875#define CLK_PCLK_SMMU_GSCL0 26876#define CLK_PCLK_SMMU_GSCL1 27877#define CLK_PCLK_SMMU_GSCL2 28878 879/* CMU_APOLLO */880#define CLK_FOUT_APOLLO_PLL 1881 882#define CLK_MOUT_APOLLO_PLL 2883#define CLK_MOUT_BUS_PLL_APOLLO_USER 3884#define CLK_MOUT_APOLLO 4885 886#define CLK_DIV_CNTCLK_APOLLO 5887#define CLK_DIV_PCLK_DBG_APOLLO 6888#define CLK_DIV_ATCLK_APOLLO 7889#define CLK_DIV_PCLK_APOLLO 8890#define CLK_DIV_ACLK_APOLLO 9891#define CLK_DIV_APOLLO2 10892#define CLK_DIV_APOLLO1 11893#define CLK_DIV_SCLK_HPM_APOLLO 12894#define CLK_DIV_APOLLO_PLL 13895 896#define CLK_ACLK_ATBDS_APOLLO_3 14897#define CLK_ACLK_ATBDS_APOLLO_2 15898#define CLK_ACLK_ATBDS_APOLLO_1 16899#define CLK_ACLK_ATBDS_APOLLO_0 17900#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18901#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19902#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20903#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21904#define CLK_ACLK_ASYNCACES_APOLLO_CCI 22905#define CLK_ACLK_AHB2APB_APOLLOP 23906#define CLK_ACLK_APOLLONP_200 24907#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25908#define CLK_PCLK_PMU_APOLLO 26909#define CLK_PCLK_SYSREG_APOLLO 27910#define CLK_CNTCLK_APOLLO 28911#define CLK_SCLK_HPM_APOLLO 29912#define CLK_SCLK_APOLLO 30913 914/* CMU_ATLAS */915#define CLK_FOUT_ATLAS_PLL 1916 917#define CLK_MOUT_ATLAS_PLL 2918#define CLK_MOUT_BUS_PLL_ATLAS_USER 3919#define CLK_MOUT_ATLAS 4920 921#define CLK_DIV_CNTCLK_ATLAS 5922#define CLK_DIV_PCLK_DBG_ATLAS 6923#define CLK_DIV_ATCLK_ATLASO 7924#define CLK_DIV_PCLK_ATLAS 8925#define CLK_DIV_ACLK_ATLAS 9926#define CLK_DIV_ATLAS2 10927#define CLK_DIV_ATLAS1 11928#define CLK_DIV_SCLK_HPM_ATLAS 12929#define CLK_DIV_ATLAS_PLL 13930 931#define CLK_ACLK_ATB_AUD_CSSYS 14932#define CLK_ACLK_ATB_APOLLO3_CSSYS 15933#define CLK_ACLK_ATB_APOLLO2_CSSYS 16934#define CLK_ACLK_ATB_APOLLO1_CSSYS 17935#define CLK_ACLK_ATB_APOLLO0_CSSYS 18936#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19937#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20938#define CLK_ACLK_ASYNCACES_ATLAS_CCI 21939#define CLK_ACLK_AHB2APB_ATLASP 22940#define CLK_ACLK_ATLASNP_200 23941#define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24942#define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25943#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26944#define CLK_PCLK_PMU_ATLAS 27945#define CLK_PCLK_SYSREG_ATLAS 28946#define CLK_PCLK_SECJTAG 29947#define CLK_CNTCLK_ATLAS 30948#define CLK_SCLK_FREQ_DET_ATLAS_PLL 31949#define CLK_SCLK_HPM_ATLAS 32950#define CLK_TRACECLK 33951#define CLK_CTMCLK 34952#define CLK_HCLK_CSSYS 35953#define CLK_PCLK_DBG_CSSYS 36954#define CLK_PCLK_DBG 37955#define CLK_ATCLK 38956#define CLK_SCLK_ATLAS 39957 958/* CMU_MSCL */959#define CLK_MOUT_SCLK_JPEG_USER 1960#define CLK_MOUT_ACLK_MSCL_400_USER 2961#define CLK_MOUT_SCLK_JPEG 3962 963#define CLK_DIV_PCLK_MSCL 4964 965#define CLK_ACLK_BTS_JPEG 5966#define CLK_ACLK_BTS_M2MSCALER1 6967#define CLK_ACLK_BTS_M2MSCALER0 7968#define CLK_ACLK_AHB2APB_MSCL0P 8969#define CLK_ACLK_XIU_MSCLX 9970#define CLK_ACLK_MSCLNP_100 10971#define CLK_ACLK_MSCLND_400 11972#define CLK_ACLK_JPEG 12973#define CLK_ACLK_M2MSCALER1 13974#define CLK_ACLK_M2MSCALER0 14975#define CLK_ACLK_SMMU_M2MSCALER0 15976#define CLK_ACLK_SMMU_M2MSCALER1 16977#define CLK_ACLK_SMMU_JPEG 17978#define CLK_PCLK_BTS_JPEG 18979#define CLK_PCLK_BTS_M2MSCALER1 19980#define CLK_PCLK_BTS_M2MSCALER0 20981#define CLK_PCLK_PMU_MSCL 21982#define CLK_PCLK_SYSREG_MSCL 22983#define CLK_PCLK_JPEG 23984#define CLK_PCLK_M2MSCALER1 24985#define CLK_PCLK_M2MSCALER0 25986#define CLK_PCLK_SMMU_M2MSCALER0 26987#define CLK_PCLK_SMMU_M2MSCALER1 27988#define CLK_PCLK_SMMU_JPEG 28989#define CLK_SCLK_JPEG 29990 991/* CMU_MFC */992#define CLK_MOUT_ACLK_MFC_400_USER 1993 994#define CLK_DIV_PCLK_MFC 2995 996#define CLK_ACLK_BTS_MFC_1 3997#define CLK_ACLK_BTS_MFC_0 4998#define CLK_ACLK_AHB2APB_MFCP 5999#define CLK_ACLK_XIU_MFCX 61000#define CLK_ACLK_MFCNP_100 71001#define CLK_ACLK_MFCND_400 81002#define CLK_ACLK_MFC 91003#define CLK_ACLK_SMMU_MFC_1 101004#define CLK_ACLK_SMMU_MFC_0 111005#define CLK_PCLK_BTS_MFC_1 121006#define CLK_PCLK_BTS_MFC_0 131007#define CLK_PCLK_PMU_MFC 141008#define CLK_PCLK_SYSREG_MFC 151009#define CLK_PCLK_MFC 161010#define CLK_PCLK_SMMU_MFC_1 171011#define CLK_PCLK_SMMU_MFC_0 181012 1013/* CMU_HEVC */1014#define CLK_MOUT_ACLK_HEVC_400_USER 11015 1016#define CLK_DIV_PCLK_HEVC 21017 1018#define CLK_ACLK_BTS_HEVC_1 31019#define CLK_ACLK_BTS_HEVC_0 41020#define CLK_ACLK_AHB2APB_HEVCP 51021#define CLK_ACLK_XIU_HEVCX 61022#define CLK_ACLK_HEVCNP_100 71023#define CLK_ACLK_HEVCND_400 81024#define CLK_ACLK_HEVC 91025#define CLK_ACLK_SMMU_HEVC_1 101026#define CLK_ACLK_SMMU_HEVC_0 111027#define CLK_PCLK_BTS_HEVC_1 121028#define CLK_PCLK_BTS_HEVC_0 131029#define CLK_PCLK_PMU_HEVC 141030#define CLK_PCLK_SYSREG_HEVC 151031#define CLK_PCLK_HEVC 161032#define CLK_PCLK_SMMU_HEVC_1 171033#define CLK_PCLK_SMMU_HEVC_0 181034 1035/* CMU_ISP */1036#define CLK_MOUT_ACLK_ISP_DIS_400_USER 11037#define CLK_MOUT_ACLK_ISP_400_USER 21038 1039#define CLK_DIV_PCLK_ISP_DIS 31040#define CLK_DIV_PCLK_ISP 41041#define CLK_DIV_ACLK_ISP_D_200 51042#define CLK_DIV_ACLK_ISP_C_200 61043 1044#define CLK_ACLK_ISP_D_GLUE 71045#define CLK_ACLK_SCALERP 81046#define CLK_ACLK_3DNR 91047#define CLK_ACLK_DIS 101048#define CLK_ACLK_SCALERC 111049#define CLK_ACLK_DRC 121050#define CLK_ACLK_ISP 131051#define CLK_ACLK_AXIUS_SCALERP 141052#define CLK_ACLK_AXIUS_SCALERC 151053#define CLK_ACLK_AXIUS_DRC 161054#define CLK_ACLK_ASYNCAHBM_ISP2P 171055#define CLK_ACLK_ASYNCAHBM_ISP1P 181056#define CLK_ACLK_ASYNCAXIS_DIS1 191057#define CLK_ACLK_ASYNCAXIS_DIS0 201058#define CLK_ACLK_ASYNCAXIM_DIS1 211059#define CLK_ACLK_ASYNCAXIM_DIS0 221060#define CLK_ACLK_ASYNCAXIM_ISP2P 231061#define CLK_ACLK_ASYNCAXIM_ISP1P 241062#define CLK_ACLK_AHB2APB_ISP2P 251063#define CLK_ACLK_AHB2APB_ISP1P 261064#define CLK_ACLK_AXI2APB_ISP2P 271065#define CLK_ACLK_AXI2APB_ISP1P 281066#define CLK_ACLK_XIU_ISPEX1 291067#define CLK_ACLK_XIU_ISPEX0 301068#define CLK_ACLK_ISPND_400 311069#define CLK_ACLK_SMMU_SCALERP 321070#define CLK_ACLK_SMMU_3DNR 331071#define CLK_ACLK_SMMU_DIS1 341072#define CLK_ACLK_SMMU_DIS0 351073#define CLK_ACLK_SMMU_SCALERC 361074#define CLK_ACLK_SMMU_DRC 371075#define CLK_ACLK_SMMU_ISP 381076#define CLK_ACLK_BTS_SCALERP 391077#define CLK_ACLK_BTS_3DR 401078#define CLK_ACLK_BTS_DIS1 411079#define CLK_ACLK_BTS_DIS0 421080#define CLK_ACLK_BTS_SCALERC 431081#define CLK_ACLK_BTS_DRC 441082#define CLK_ACLK_BTS_ISP 451083#define CLK_PCLK_SMMU_SCALERP 461084#define CLK_PCLK_SMMU_3DNR 471085#define CLK_PCLK_SMMU_DIS1 481086#define CLK_PCLK_SMMU_DIS0 491087#define CLK_PCLK_SMMU_SCALERC 501088#define CLK_PCLK_SMMU_DRC 511089#define CLK_PCLK_SMMU_ISP 521090#define CLK_PCLK_BTS_SCALERP 531091#define CLK_PCLK_BTS_3DNR 541092#define CLK_PCLK_BTS_DIS1 551093#define CLK_PCLK_BTS_DIS0 561094#define CLK_PCLK_BTS_SCALERC 571095#define CLK_PCLK_BTS_DRC 581096#define CLK_PCLK_BTS_ISP 591097#define CLK_PCLK_ASYNCAXI_DIS1 601098#define CLK_PCLK_ASYNCAXI_DIS0 611099#define CLK_PCLK_PMU_ISP 621100#define CLK_PCLK_SYSREG_ISP 631101#define CLK_PCLK_CMU_ISP_LOCAL 641102#define CLK_PCLK_SCALERP 651103#define CLK_PCLK_3DNR 661104#define CLK_PCLK_DIS_CORE 671105#define CLK_PCLK_DIS 681106#define CLK_PCLK_SCALERC 691107#define CLK_PCLK_DRC 701108#define CLK_PCLK_ISP 711109#define CLK_SCLK_PIXELASYNCS_DIS 721110#define CLK_SCLK_PIXELASYNCM_DIS 731111#define CLK_SCLK_PIXELASYNCS_SCALERP 741112#define CLK_SCLK_PIXELASYNCM_ISPD 751113#define CLK_SCLK_PIXELASYNCS_ISPC 761114#define CLK_SCLK_PIXELASYNCM_ISPC 771115 1116/* CMU_CAM0 */1117#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 11118#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 21119 1120#define CLK_MOUT_ACLK_CAM0_333_USER 31121#define CLK_MOUT_ACLK_CAM0_400_USER 41122#define CLK_MOUT_ACLK_CAM0_552_USER 51123#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 61124#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 71125#define CLK_MOUT_ACLK_LITE_D_B 81126#define CLK_MOUT_ACLK_LITE_D_A 91127#define CLK_MOUT_ACLK_LITE_B_B 101128#define CLK_MOUT_ACLK_LITE_B_A 111129#define CLK_MOUT_ACLK_LITE_A_B 121130#define CLK_MOUT_ACLK_LITE_A_A 131131#define CLK_MOUT_ACLK_CAM0_400 141132#define CLK_MOUT_ACLK_CSIS1_B 151133#define CLK_MOUT_ACLK_CSIS1_A 161134#define CLK_MOUT_ACLK_CSIS0_B 171135#define CLK_MOUT_ACLK_CSIS0_A 181136#define CLK_MOUT_ACLK_3AA1_B 191137#define CLK_MOUT_ACLK_3AA1_A 201138#define CLK_MOUT_ACLK_3AA0_B 211139#define CLK_MOUT_ACLK_3AA0_A 221140#define CLK_MOUT_SCLK_LITE_FREECNT_C 231141#define CLK_MOUT_SCLK_LITE_FREECNT_B 241142#define CLK_MOUT_SCLK_LITE_FREECNT_A 251143#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 261144#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 271145#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 281146#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 291147 1148#define CLK_DIV_PCLK_CAM0_50 301149#define CLK_DIV_ACLK_CAM0_200 311150#define CLK_DIV_ACLK_CAM0_BUS_400 321151#define CLK_DIV_PCLK_LITE_D 331152#define CLK_DIV_ACLK_LITE_D 341153#define CLK_DIV_PCLK_LITE_B 351154#define CLK_DIV_ACLK_LITE_B 361155#define CLK_DIV_PCLK_LITE_A 371156#define CLK_DIV_ACLK_LITE_A 381157#define CLK_DIV_ACLK_CSIS1 391158#define CLK_DIV_ACLK_CSIS0 401159#define CLK_DIV_PCLK_3AA1 411160#define CLK_DIV_ACLK_3AA1 421161#define CLK_DIV_PCLK_3AA0 431162#define CLK_DIV_ACLK_3AA0 441163#define CLK_DIV_SCLK_PIXELASYNC_LITE_C 451164#define CLK_DIV_PCLK_PIXELASYNC_LITE_C 461165#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 471166 1167#define CLK_ACLK_CSIS1 501168#define CLK_ACLK_CSIS0 511169#define CLK_ACLK_3AA1 521170#define CLK_ACLK_3AA0 531171#define CLK_ACLK_LITE_D 541172#define CLK_ACLK_LITE_B 551173#define CLK_ACLK_LITE_A 561174#define CLK_ACLK_AHBSYNCDN 571175#define CLK_ACLK_AXIUS_LITE_D 581176#define CLK_ACLK_AXIUS_LITE_B 591177#define CLK_ACLK_AXIUS_LITE_A 601178#define CLK_ACLK_ASYNCAPBM_3AA1 611179#define CLK_ACLK_ASYNCAPBS_3AA1 621180#define CLK_ACLK_ASYNCAPBM_3AA0 631181#define CLK_ACLK_ASYNCAPBS_3AA0 641182#define CLK_ACLK_ASYNCAPBM_LITE_D 651183#define CLK_ACLK_ASYNCAPBS_LITE_D 661184#define CLK_ACLK_ASYNCAPBM_LITE_B 671185#define CLK_ACLK_ASYNCAPBS_LITE_B 681186#define CLK_ACLK_ASYNCAPBM_LITE_A 691187#define CLK_ACLK_ASYNCAPBS_LITE_A 701188#define CLK_ACLK_ASYNCAXIM_ISP0P 711189#define CLK_ACLK_ASYNCAXIM_3AA1 721190#define CLK_ACLK_ASYNCAXIS_3AA1 731191#define CLK_ACLK_ASYNCAXIM_3AA0 741192#define CLK_ACLK_ASYNCAXIS_3AA0 751193#define CLK_ACLK_ASYNCAXIM_LITE_D 761194#define CLK_ACLK_ASYNCAXIS_LITE_D 771195#define CLK_ACLK_ASYNCAXIM_LITE_B 781196#define CLK_ACLK_ASYNCAXIS_LITE_B 791197#define CLK_ACLK_ASYNCAXIM_LITE_A 801198#define CLK_ACLK_ASYNCAXIS_LITE_A 811199#define CLK_ACLK_AHB2APB_ISPSFRP 821200#define CLK_ACLK_AXI2APB_ISP0P 831201#define CLK_ACLK_AXI2AHB_ISP0P 841202#define CLK_ACLK_XIU_IS0X 851203#define CLK_ACLK_XIU_ISP0EX 861204#define CLK_ACLK_CAM0NP_276 871205#define CLK_ACLK_CAM0ND_400 881206#define CLK_ACLK_SMMU_3AA1 891207#define CLK_ACLK_SMMU_3AA0 901208#define CLK_ACLK_SMMU_LITE_D 911209#define CLK_ACLK_SMMU_LITE_B 921210#define CLK_ACLK_SMMU_LITE_A 931211#define CLK_ACLK_BTS_3AA1 941212#define CLK_ACLK_BTS_3AA0 951213#define CLK_ACLK_BTS_LITE_D 961214#define CLK_ACLK_BTS_LITE_B 971215#define CLK_ACLK_BTS_LITE_A 981216#define CLK_PCLK_SMMU_3AA1 991217#define CLK_PCLK_SMMU_3AA0 1001218#define CLK_PCLK_SMMU_LITE_D 1011219#define CLK_PCLK_SMMU_LITE_B 1021220#define CLK_PCLK_SMMU_LITE_A 1031221#define CLK_PCLK_BTS_3AA1 1041222#define CLK_PCLK_BTS_3AA0 1051223#define CLK_PCLK_BTS_LITE_D 1061224#define CLK_PCLK_BTS_LITE_B 1071225#define CLK_PCLK_BTS_LITE_A 1081226#define CLK_PCLK_ASYNCAXI_CAM1 1091227#define CLK_PCLK_ASYNCAXI_3AA1 1101228#define CLK_PCLK_ASYNCAXI_3AA0 1111229#define CLK_PCLK_ASYNCAXI_LITE_D 1121230#define CLK_PCLK_ASYNCAXI_LITE_B 1131231#define CLK_PCLK_ASYNCAXI_LITE_A 1141232#define CLK_PCLK_PMU_CAM0 1151233#define CLK_PCLK_SYSREG_CAM0 1161234#define CLK_PCLK_CMU_CAM0_LOCAL 1171235#define CLK_PCLK_CSIS1 1181236#define CLK_PCLK_CSIS0 1191237#define CLK_PCLK_3AA1 1201238#define CLK_PCLK_3AA0 1211239#define CLK_PCLK_LITE_D 1221240#define CLK_PCLK_LITE_B 1231241#define CLK_PCLK_LITE_A 1241242#define CLK_PHYCLK_RXBYTECLKHS0_S4 1251243#define CLK_PHYCLK_RXBYTECLKHS0_S2A 1261244#define CLK_SCLK_LITE_FREECNT 1271245#define CLK_SCLK_PIXELASYNCM_3AA1 1281246#define CLK_SCLK_PIXELASYNCM_3AA0 1291247#define CLK_SCLK_PIXELASYNCS_3AA0 1301248#define CLK_SCLK_PIXELASYNCM_LITE_C 1311249#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 1321250#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 1331251 1252/* CMU_CAM1 */1253#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 11254 1255#define CLK_MOUT_SCLK_ISP_UART_USER 21256#define CLK_MOUT_SCLK_ISP_SPI1_USER 31257#define CLK_MOUT_SCLK_ISP_SPI0_USER 41258#define CLK_MOUT_ACLK_CAM1_333_USER 51259#define CLK_MOUT_ACLK_CAM1_400_USER 61260#define CLK_MOUT_ACLK_CAM1_552_USER 71261#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 81262#define CLK_MOUT_ACLK_CSIS2_B 91263#define CLK_MOUT_ACLK_CSIS2_A 101264#define CLK_MOUT_ACLK_FD_B 111265#define CLK_MOUT_ACLK_FD_A 121266#define CLK_MOUT_ACLK_LITE_C_B 131267#define CLK_MOUT_ACLK_LITE_C_A 141268 1269#define CLK_DIV_SCLK_ISP_MPWM 151270#define CLK_DIV_PCLK_CAM1_83 161271#define CLK_DIV_PCLK_CAM1_166 171272#define CLK_DIV_PCLK_DBG_CAM1 181273#define CLK_DIV_ATCLK_CAM1 191274#define CLK_DIV_ACLK_CSIS2 201275#define CLK_DIV_PCLK_FD 211276#define CLK_DIV_ACLK_FD 221277#define CLK_DIV_PCLK_LITE_C 231278#define CLK_DIV_ACLK_LITE_C 241279 1280#define CLK_ACLK_ISP_GIC 251281#define CLK_ACLK_FD 261282#define CLK_ACLK_LITE_C 271283#define CLK_ACLK_CSIS2 281284#define CLK_ACLK_ASYNCAPBM_FD 291285#define CLK_ACLK_ASYNCAPBS_FD 301286#define CLK_ACLK_ASYNCAPBM_LITE_C 311287#define CLK_ACLK_ASYNCAPBS_LITE_C 321288#define CLK_ACLK_ASYNCAHBS_SFRISP2H2 331289#define CLK_ACLK_ASYNCAHBS_SFRISP2H1 341290#define CLK_ACLK_ASYNCAXIM_CA5 351291#define CLK_ACLK_ASYNCAXIS_CA5 361292#define CLK_ACLK_ASYNCAXIS_ISPX2 371293#define CLK_ACLK_ASYNCAXIS_ISPX1 381294#define CLK_ACLK_ASYNCAXIS_ISPX0 391295#define CLK_ACLK_ASYNCAXIM_ISPEX 401296#define CLK_ACLK_ASYNCAXIM_ISP3P 411297#define CLK_ACLK_ASYNCAXIS_ISP3P 421298#define CLK_ACLK_ASYNCAXIM_FD 431299#define CLK_ACLK_ASYNCAXIS_FD 441300#define CLK_ACLK_ASYNCAXIM_LITE_C 451301#define CLK_ACLK_ASYNCAXIS_LITE_C 461302#define CLK_ACLK_AHB2APB_ISP5P 471303#define CLK_ACLK_AHB2APB_ISP3P 481304#define CLK_ACLK_AXI2APB_ISP3P 491305#define CLK_ACLK_AHB_SFRISP2H 501306#define CLK_ACLK_AXI_ISP_HX_R 511307#define CLK_ACLK_AXI_ISP_CX_R 521308#define CLK_ACLK_AXI_ISP_HX 531309#define CLK_ACLK_AXI_ISP_CX 541310#define CLK_ACLK_XIU_ISPX 551311#define CLK_ACLK_XIU_ISPEX 561312#define CLK_ACLK_CAM1NP_333 571313#define CLK_ACLK_CAM1ND_400 581314#define CLK_ACLK_SMMU_ISPCPU 591315#define CLK_ACLK_SMMU_FD 601316#define CLK_ACLK_SMMU_LITE_C 611317#define CLK_ACLK_BTS_ISP3P 621318#define CLK_ACLK_BTS_FD 631319#define CLK_ACLK_BTS_LITE_C 641320#define CLK_ACLK_AHBDN_SFRISP2H 651321#define CLK_ACLK_AHBDN_ISP5P 661322#define CLK_ACLK_AXIUS_ISP3P 671323#define CLK_ACLK_AXIUS_FD 681324#define CLK_ACLK_AXIUS_LITE_C 691325#define CLK_PCLK_SMMU_ISPCPU 701326#define CLK_PCLK_SMMU_FD 711327#define CLK_PCLK_SMMU_LITE_C 721328#define CLK_PCLK_BTS_ISP3P 731329#define CLK_PCLK_BTS_FD 741330#define CLK_PCLK_BTS_LITE_C 751331#define CLK_PCLK_ASYNCAXIM_CA5 761332#define CLK_PCLK_ASYNCAXIM_ISPEX 771333#define CLK_PCLK_ASYNCAXIM_ISP3P 781334#define CLK_PCLK_ASYNCAXIM_FD 791335#define CLK_PCLK_ASYNCAXIM_LITE_C 801336#define CLK_PCLK_PMU_CAM1 811337#define CLK_PCLK_SYSREG_CAM1 821338#define CLK_PCLK_CMU_CAM1_LOCAL 831339#define CLK_PCLK_ISP_MCTADC 841340#define CLK_PCLK_ISP_WDT 851341#define CLK_PCLK_ISP_PWM 861342#define CLK_PCLK_ISP_UART 871343#define CLK_PCLK_ISP_MCUCTL 881344#define CLK_PCLK_ISP_SPI1 891345#define CLK_PCLK_ISP_SPI0 901346#define CLK_PCLK_ISP_I2C2 911347#define CLK_PCLK_ISP_I2C1 921348#define CLK_PCLK_ISP_I2C0 931349#define CLK_PCLK_ISP_MPWM 941350#define CLK_PCLK_FD 951351#define CLK_PCLK_LITE_C 961352#define CLK_PCLK_CSIS2 971353#define CLK_SCLK_ISP_I2C2 981354#define CLK_SCLK_ISP_I2C1 991355#define CLK_SCLK_ISP_I2C0 1001356#define CLK_SCLK_ISP_PWM 1011357#define CLK_PHYCLK_RXBYTECLKHS0_S2B 1021358#define CLK_SCLK_LITE_C_FREECNT 1031359#define CLK_SCLK_PIXELASYNCM_FD 1041360#define CLK_SCLK_ISP_MCTADC 1051361#define CLK_SCLK_ISP_UART 1061362#define CLK_SCLK_ISP_SPI1 1071363#define CLK_SCLK_ISP_SPI0 1081364#define CLK_SCLK_ISP_MPWM 1091365#define CLK_PCLK_DBG_ISP 1101366#define CLK_ATCLK_ISP 1111367#define CLK_SCLK_ISP_CA5 1121368 1369/* CMU_IMEM */1370#define CLK_ACLK_SLIMSSS 21371#define CLK_PCLK_SLIMSSS 351372 1373#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */1374