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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.4 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>5 */6 7#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H8#define _DT_BINDINGS_CLOCK_EXYNOS7_H9 10/* TOPC */11#define DOUT_ACLK_PERIS 112#define DOUT_SCLK_BUS0_PLL 213#define DOUT_SCLK_BUS1_PLL 314#define DOUT_SCLK_CC_PLL 415#define DOUT_SCLK_MFC_PLL 516#define DOUT_ACLK_CCORE_133 617#define DOUT_ACLK_MSCL_532 718#define ACLK_MSCL_532 819#define DOUT_SCLK_AUD_PLL 920#define FOUT_AUD_PLL 1021#define SCLK_AUD_PLL 1122#define SCLK_MFC_PLL_B 1223#define SCLK_MFC_PLL_A 1324#define SCLK_BUS1_PLL_B 1425#define SCLK_BUS1_PLL_A 1526#define SCLK_BUS0_PLL_B 1627#define SCLK_BUS0_PLL_A 1728#define SCLK_CC_PLL_B 1829#define SCLK_CC_PLL_A 1930#define ACLK_CCORE_133 2031#define ACLK_PERIS_66 2132#define TOPC_NR_CLK 2233 34/* TOP0 */35#define DOUT_ACLK_PERIC1 136#define DOUT_ACLK_PERIC0 237#define CLK_SCLK_UART0 338#define CLK_SCLK_UART1 439#define CLK_SCLK_UART2 540#define CLK_SCLK_UART3 641#define CLK_SCLK_SPI0 742#define CLK_SCLK_SPI1 843#define CLK_SCLK_SPI2 944#define CLK_SCLK_SPI3 1045#define CLK_SCLK_SPI4 1146#define CLK_SCLK_SPDIF 1247#define CLK_SCLK_PCM1 1348#define CLK_SCLK_I2S1 1449#define CLK_ACLK_PERIC0_66 1550#define CLK_ACLK_PERIC1_66 1651#define TOP0_NR_CLK 1752 53/* TOP1 */54#define DOUT_ACLK_FSYS1_200 155#define DOUT_ACLK_FSYS0_200 256#define DOUT_SCLK_MMC2 357#define DOUT_SCLK_MMC1 458#define DOUT_SCLK_MMC0 559#define CLK_SCLK_MMC2 660#define CLK_SCLK_MMC1 761#define CLK_SCLK_MMC0 862#define CLK_ACLK_FSYS0_200 963#define CLK_ACLK_FSYS1_200 1064#define CLK_SCLK_PHY_FSYS1 1165#define CLK_SCLK_PHY_FSYS1_26M 1266#define MOUT_SCLK_UFSUNIPRO20 1367#define DOUT_SCLK_UFSUNIPRO20 1468#define CLK_SCLK_UFSUNIPRO20 1569#define DOUT_SCLK_PHY_FSYS1 1670#define DOUT_SCLK_PHY_FSYS1_26M 1771#define TOP1_NR_CLK 1872 73/* CCORE */74#define PCLK_RTC 175#define CCORE_NR_CLK 276 77/* PERIC0 */78#define PCLK_UART0 179#define SCLK_UART0 280#define PCLK_HSI2C0 381#define PCLK_HSI2C1 482#define PCLK_HSI2C4 583#define PCLK_HSI2C5 684#define PCLK_HSI2C9 785#define PCLK_HSI2C10 886#define PCLK_HSI2C11 987#define PCLK_PWM 1088#define SCLK_PWM 1189#define PCLK_ADCIF 1290#define PERIC0_NR_CLK 1391 92/* PERIC1 */93#define PCLK_UART1 194#define PCLK_UART2 295#define PCLK_UART3 396#define SCLK_UART1 497#define SCLK_UART2 598#define SCLK_UART3 699#define PCLK_HSI2C2 7100#define PCLK_HSI2C3 8101#define PCLK_HSI2C6 9102#define PCLK_HSI2C7 10103#define PCLK_HSI2C8 11104#define PCLK_SPI0 12105#define PCLK_SPI1 13106#define PCLK_SPI2 14107#define PCLK_SPI3 15108#define PCLK_SPI4 16109#define SCLK_SPI0 17110#define SCLK_SPI1 18111#define SCLK_SPI2 19112#define SCLK_SPI3 20113#define SCLK_SPI4 21114#define PCLK_I2S1 22115#define PCLK_PCM1 23116#define PCLK_SPDIF 24117#define SCLK_I2S1 25118#define SCLK_PCM1 26119#define SCLK_SPDIF 27120#define PERIC1_NR_CLK 28121 122/* PERIS */123#define PCLK_CHIPID 1124#define SCLK_CHIPID 2125#define PCLK_WDT 3126#define PCLK_TMU 4127#define SCLK_TMU 5128#define PERIS_NR_CLK 6129 130/* FSYS0 */131#define ACLK_MMC2 1132#define ACLK_AXIUS_USBDRD30X_FSYS0X 2133#define ACLK_USBDRD300 3134#define SCLK_USBDRD300_SUSPENDCLK 4135#define SCLK_USBDRD300_REFCLK 5136#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6137#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7138#define OSCCLK_PHY_CLKOUT_USB30_PHY 8139#define ACLK_PDMA0 9140#define ACLK_PDMA1 10141#define FSYS0_NR_CLK 11142 143/* FSYS1 */144#define ACLK_MMC1 1145#define ACLK_MMC0 2146#define PHYCLK_UFS20_TX0_SYMBOL 3147#define PHYCLK_UFS20_RX0_SYMBOL 4148#define PHYCLK_UFS20_RX1_SYMBOL 5149#define ACLK_UFS20_LINK 6150#define SCLK_UFSUNIPRO20_USER 7151#define PHYCLK_UFS20_RX1_SYMBOL_USER 8152#define PHYCLK_UFS20_RX0_SYMBOL_USER 9153#define PHYCLK_UFS20_TX0_SYMBOL_USER 10154#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11155#define SCLK_COMBO_PHY_EMBEDDED_26M 12156#define DOUT_PCLK_FSYS1 13157#define PCLK_GPIO_FSYS1 14158#define MOUT_FSYS1_PHYCLK_SEL1 15159#define FSYS1_NR_CLK 16160 161/* MSCL */162#define USERMUX_ACLK_MSCL_532 1163#define DOUT_PCLK_MSCL 2164#define ACLK_MSCL_0 3165#define ACLK_MSCL_1 4166#define ACLK_JPEG 5167#define ACLK_G2D 6168#define ACLK_LH_ASYNC_SI_MSCL_0 7169#define ACLK_LH_ASYNC_SI_MSCL_1 8170#define ACLK_AXI2ACEL_BRIDGE 9171#define ACLK_XIU_MSCLX_0 10172#define ACLK_XIU_MSCLX_1 11173#define ACLK_QE_MSCL_0 12174#define ACLK_QE_MSCL_1 13175#define ACLK_QE_JPEG 14176#define ACLK_QE_G2D 15177#define ACLK_PPMU_MSCL_0 16178#define ACLK_PPMU_MSCL_1 17179#define ACLK_MSCLNP_133 18180#define ACLK_AHB2APB_MSCL0P 19181#define ACLK_AHB2APB_MSCL1P 20182 183#define PCLK_MSCL_0 21184#define PCLK_MSCL_1 22185#define PCLK_JPEG 23186#define PCLK_G2D 24187#define PCLK_QE_MSCL_0 25188#define PCLK_QE_MSCL_1 26189#define PCLK_QE_JPEG 27190#define PCLK_QE_G2D 28191#define PCLK_PPMU_MSCL_0 29192#define PCLK_PPMU_MSCL_1 30193#define PCLK_AXI2ACEL_BRIDGE 31194#define PCLK_PMU_MSCL 32195#define MSCL_NR_CLK 33196 197/* AUD */198#define SCLK_I2S 1199#define SCLK_PCM 2200#define PCLK_I2S 3201#define PCLK_PCM 4202#define ACLK_ADMA 5203#define AUD_NR_CLK 6204#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */205