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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.4 * https://www.samsung.com5 * Copyright (c) 2017-2022 Tesla, Inc.6 * https://www.tesla.com7 *8 * The constants defined in this header are being used in dts9 * and fsd platform driver.10 */11 12#ifndef _DT_BINDINGS_CLOCK_FSD_H13#define _DT_BINDINGS_CLOCK_FSD_H14 15/* CMU */16#define DOUT_CMU_PLL_SHARED0_DIV4 117#define DOUT_CMU_PERIC_SHARED1DIV36 218#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 319#define DOUT_CMU_PERIC_SHARED0DIV20 420#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 521#define DOUT_CMU_PLL_SHARED0_DIV6 622#define DOUT_CMU_FSYS0_SHARED1DIV4 723#define DOUT_CMU_FSYS0_SHARED0DIV4 824#define DOUT_CMU_FSYS1_SHARED0DIV8 925#define DOUT_CMU_FSYS1_SHARED0DIV4 1026#define CMU_CPUCL_SWITCH_GATE 1127#define DOUT_CMU_IMEM_TCUCLK 1228#define DOUT_CMU_IMEM_ACLK 1329#define DOUT_CMU_IMEM_DMACLK 1430#define GAT_CMU_FSYS0_SHARED0DIV4 1531#define CMU_NR_CLK 1632 33/* PERIC */34#define PERIC_SCLK_UART0 135#define PERIC_PCLK_UART0 236#define PERIC_SCLK_UART1 337#define PERIC_PCLK_UART1 438#define PERIC_DMA0_IPCLKPORT_ACLK 539#define PERIC_DMA1_IPCLKPORT_ACLK 640#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 741#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 842#define PERIC_PCLK_SPI0 943#define PERIC_SCLK_SPI0 1044#define PERIC_PCLK_SPI1 1145#define PERIC_SCLK_SPI1 1246#define PERIC_PCLK_SPI2 1347#define PERIC_SCLK_SPI2 1448#define PERIC_PCLK_TDM0 1549#define PERIC_PCLK_HSI2C0 1650#define PERIC_PCLK_HSI2C1 1751#define PERIC_PCLK_HSI2C2 1852#define PERIC_PCLK_HSI2C3 1953#define PERIC_PCLK_HSI2C4 2054#define PERIC_PCLK_HSI2C5 2155#define PERIC_PCLK_HSI2C6 2256#define PERIC_PCLK_HSI2C7 2357#define PERIC_MCAN0_IPCLKPORT_CCLK 2458#define PERIC_MCAN0_IPCLKPORT_PCLK 2559#define PERIC_MCAN1_IPCLKPORT_CCLK 2660#define PERIC_MCAN1_IPCLKPORT_PCLK 2761#define PERIC_MCAN2_IPCLKPORT_CCLK 2862#define PERIC_MCAN2_IPCLKPORT_PCLK 2963#define PERIC_MCAN3_IPCLKPORT_CCLK 3064#define PERIC_MCAN3_IPCLKPORT_PCLK 3165#define PERIC_PCLK_ADCIF 3266#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 3367#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 3468#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 3569#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 3670#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 3771#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 3872#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 3973#define PERIC_HCLK_TDM0 4074#define PERIC_PCLK_TDM1 4175#define PERIC_HCLK_TDM1 4276#define PERIC_EQOS_PHYRXCLK_MUX 4377#define PERIC_EQOS_PHYRXCLK 4478#define PERIC_DOUT_RGMII_CLK 4579#define PERIC_NR_CLK 4680 81/* FSYS0 */82#define UFS0_MPHY_REFCLK_IXTAL24 183#define UFS0_MPHY_REFCLK_IXTAL26 284#define UFS1_MPHY_REFCLK_IXTAL24 385#define UFS1_MPHY_REFCLK_IXTAL26 486#define UFS0_TOP0_HCLK_BUS 587#define UFS0_TOP0_ACLK 688#define UFS0_TOP0_CLK_UNIPRO 789#define UFS0_TOP0_FMP_CLK 890#define UFS1_TOP1_HCLK_BUS 991#define UFS1_TOP1_ACLK 1092#define UFS1_TOP1_CLK_UNIPRO 1193#define UFS1_TOP1_FMP_CLK 1294#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 1395#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 1496#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 1597#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 1698#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 1799#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18100#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19101#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20102#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21103#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22104#define FSYS0_NR_CLK 23105 106/* FSYS1 */107#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1108#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2109#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3110#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4111#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5112#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6113#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7114#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8115#define FSYS1_NR_CLK 9116 117/* IMEM */118#define IMEM_DMA0_IPCLKPORT_ACLK 1119#define IMEM_DMA1_IPCLKPORT_ACLK 2120#define IMEM_WDT0_IPCLKPORT_PCLK 3121#define IMEM_WDT1_IPCLKPORT_PCLK 4122#define IMEM_WDT2_IPCLKPORT_PCLK 5123#define IMEM_MCT_PCLK 6124#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7125#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8126#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9127#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10128#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11129#define IMEM_NR_CLK 12130 131/* MFC */132#define MFC_MFC_IPCLKPORT_ACLK 1133#define MFC_NR_CLK 2134 135/* CAM_CSI */136#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1137#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2138#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3139#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4140#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5141#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6142#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7143#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8144#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9145#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10146#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11147#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12148#define CAM_CSI_NR_CLK 13149 150#endif /*_DT_BINDINGS_CLOCK_FSD_H */151