292 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ OR MIT */2/*3 * Meson-G12A clock tree IDs4 *5 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.6 */7 8#ifndef __G12A_CLKC_H9#define __G12A_CLKC_H10 11#define CLKID_SYS_PLL 012#define CLKID_FIXED_PLL 113#define CLKID_FCLK_DIV2 214#define CLKID_FCLK_DIV3 315#define CLKID_FCLK_DIV4 416#define CLKID_FCLK_DIV5 517#define CLKID_FCLK_DIV7 618#define CLKID_GP0_PLL 719#define CLKID_MPEG_SEL 820#define CLKID_MPEG_DIV 921#define CLKID_CLK81 1022#define CLKID_MPLL0 1123#define CLKID_MPLL1 1224#define CLKID_MPLL2 1325#define CLKID_MPLL3 1426#define CLKID_DDR 1527#define CLKID_DOS 1628#define CLKID_AUDIO_LOCKER 1729#define CLKID_MIPI_DSI_HOST 1830#define CLKID_ETH_PHY 1931#define CLKID_ISA 2032#define CLKID_PL301 2133#define CLKID_PERIPHS 2234#define CLKID_SPICC0 2335#define CLKID_I2C 2436#define CLKID_SANA 2537#define CLKID_SD 2638#define CLKID_RNG0 2739#define CLKID_UART0 2840#define CLKID_SPICC1 2941#define CLKID_HIU_IFACE 3042#define CLKID_MIPI_DSI_PHY 3143#define CLKID_ASSIST_MISC 3244#define CLKID_SD_EMMC_A 3345#define CLKID_SD_EMMC_B 3446#define CLKID_SD_EMMC_C 3547#define CLKID_AUDIO_CODEC 3648#define CLKID_AUDIO 3749#define CLKID_ETH 3850#define CLKID_DEMUX 3951#define CLKID_AUDIO_IFIFO 4052#define CLKID_ADC 4153#define CLKID_UART1 4254#define CLKID_G2D 4355#define CLKID_RESET 4456#define CLKID_PCIE_COMB 4557#define CLKID_PARSER 4658#define CLKID_USB 4759#define CLKID_PCIE_PHY 4860#define CLKID_AHB_ARB0 4961#define CLKID_AHB_DATA_BUS 5062#define CLKID_AHB_CTRL_BUS 5163#define CLKID_HTX_HDCP22 5264#define CLKID_HTX_PCLK 5365#define CLKID_BT656 5466#define CLKID_USB1_DDR_BRIDGE 5567#define CLKID_MMC_PCLK 5668#define CLKID_UART2 5769#define CLKID_VPU_INTR 5870#define CLKID_GIC 5971#define CLKID_SD_EMMC_A_CLK0 6072#define CLKID_SD_EMMC_B_CLK0 6173#define CLKID_SD_EMMC_C_CLK0 6274#define CLKID_SD_EMMC_A_CLK0_SEL 6375#define CLKID_SD_EMMC_A_CLK0_DIV 6476#define CLKID_SD_EMMC_B_CLK0_SEL 6577#define CLKID_SD_EMMC_B_CLK0_DIV 6678#define CLKID_SD_EMMC_C_CLK0_SEL 6779#define CLKID_SD_EMMC_C_CLK0_DIV 6880#define CLKID_MPLL0_DIV 6981#define CLKID_MPLL1_DIV 7082#define CLKID_MPLL2_DIV 7183#define CLKID_MPLL3_DIV 7284#define CLKID_MPLL_PREDIV 7385#define CLKID_HIFI_PLL 7486#define CLKID_FCLK_DIV2_DIV 7587#define CLKID_FCLK_DIV3_DIV 7688#define CLKID_FCLK_DIV4_DIV 7789#define CLKID_FCLK_DIV5_DIV 7890#define CLKID_FCLK_DIV7_DIV 7991#define CLKID_VCLK2_VENCI0 8092#define CLKID_VCLK2_VENCI1 8193#define CLKID_VCLK2_VENCP0 8294#define CLKID_VCLK2_VENCP1 8395#define CLKID_VCLK2_VENCT0 8496#define CLKID_VCLK2_VENCT1 8597#define CLKID_VCLK2_OTHER 8698#define CLKID_VCLK2_ENCI 8799#define CLKID_VCLK2_ENCP 88100#define CLKID_DAC_CLK 89101#define CLKID_AOCLK 90102#define CLKID_IEC958 91103#define CLKID_ENC480P 92104#define CLKID_RNG1 93105#define CLKID_VCLK2_ENCT 94106#define CLKID_VCLK2_ENCL 95107#define CLKID_VCLK2_VENCLMMC 96108#define CLKID_VCLK2_VENCL 97109#define CLKID_VCLK2_OTHER1 98110#define CLKID_FCLK_DIV2P5 99111#define CLKID_FCLK_DIV2P5_DIV 100112#define CLKID_FIXED_PLL_DCO 101113#define CLKID_SYS_PLL_DCO 102114#define CLKID_GP0_PLL_DCO 103115#define CLKID_HIFI_PLL_DCO 104116#define CLKID_DMA 105117#define CLKID_EFUSE 106118#define CLKID_ROM_BOOT 107119#define CLKID_RESET_SEC 108120#define CLKID_SEC_AHB_APB3 109121#define CLKID_VPU_0_SEL 110122#define CLKID_VPU_0_DIV 111123#define CLKID_VPU_0 112124#define CLKID_VPU_1_SEL 113125#define CLKID_VPU_1_DIV 114126#define CLKID_VPU_1 115127#define CLKID_VPU 116128#define CLKID_VAPB_0_SEL 117129#define CLKID_VAPB_0_DIV 118130#define CLKID_VAPB_0 119131#define CLKID_VAPB_1_SEL 120132#define CLKID_VAPB_1_DIV 121133#define CLKID_VAPB_1 122134#define CLKID_VAPB_SEL 123135#define CLKID_VAPB 124136#define CLKID_HDMI_PLL_DCO 125137#define CLKID_HDMI_PLL_OD 126138#define CLKID_HDMI_PLL_OD2 127139#define CLKID_HDMI_PLL 128140#define CLKID_VID_PLL 129141#define CLKID_VID_PLL_SEL 130142#define CLKID_VID_PLL_DIV 131143#define CLKID_VCLK_SEL 132144#define CLKID_VCLK2_SEL 133145#define CLKID_VCLK_INPUT 134146#define CLKID_VCLK2_INPUT 135147#define CLKID_VCLK_DIV 136148#define CLKID_VCLK2_DIV 137149#define CLKID_VCLK 138150#define CLKID_VCLK2 139151#define CLKID_VCLK_DIV2_EN 140152#define CLKID_VCLK_DIV4_EN 141153#define CLKID_VCLK_DIV6_EN 142154#define CLKID_VCLK_DIV12_EN 143155#define CLKID_VCLK2_DIV2_EN 144156#define CLKID_VCLK2_DIV4_EN 145157#define CLKID_VCLK2_DIV6_EN 146158#define CLKID_VCLK2_DIV12_EN 147159#define CLKID_VCLK_DIV1 148160#define CLKID_VCLK_DIV2 149161#define CLKID_VCLK_DIV4 150162#define CLKID_VCLK_DIV6 151163#define CLKID_VCLK_DIV12 152164#define CLKID_VCLK2_DIV1 153165#define CLKID_VCLK2_DIV2 154166#define CLKID_VCLK2_DIV4 155167#define CLKID_VCLK2_DIV6 156168#define CLKID_VCLK2_DIV12 157169#define CLKID_CTS_ENCI_SEL 158170#define CLKID_CTS_ENCP_SEL 159171#define CLKID_CTS_VDAC_SEL 160172#define CLKID_HDMI_TX_SEL 161173#define CLKID_CTS_ENCI 162174#define CLKID_CTS_ENCP 163175#define CLKID_CTS_VDAC 164176#define CLKID_HDMI_TX 165177#define CLKID_HDMI_SEL 166178#define CLKID_HDMI_DIV 167179#define CLKID_HDMI 168180#define CLKID_MALI_0_SEL 169181#define CLKID_MALI_0_DIV 170182#define CLKID_MALI_0 171183#define CLKID_MALI_1_SEL 172184#define CLKID_MALI_1_DIV 173185#define CLKID_MALI_1 174186#define CLKID_MALI 175187#define CLKID_MPLL_50M_DIV 176188#define CLKID_MPLL_50M 177189#define CLKID_SYS_PLL_DIV16_EN 178190#define CLKID_SYS_PLL_DIV16 179191#define CLKID_CPU_CLK_DYN0_SEL 180192#define CLKID_CPU_CLK_DYN0_DIV 181193#define CLKID_CPU_CLK_DYN0 182194#define CLKID_CPU_CLK_DYN1_SEL 183195#define CLKID_CPU_CLK_DYN1_DIV 184196#define CLKID_CPU_CLK_DYN1 185197#define CLKID_CPU_CLK_DYN 186198#define CLKID_CPU_CLK 187199#define CLKID_CPU_CLK_DIV16_EN 188200#define CLKID_CPU_CLK_DIV16 189201#define CLKID_CPU_CLK_APB_DIV 190202#define CLKID_CPU_CLK_APB 191203#define CLKID_CPU_CLK_ATB_DIV 192204#define CLKID_CPU_CLK_ATB 193205#define CLKID_CPU_CLK_AXI_DIV 194206#define CLKID_CPU_CLK_AXI 195207#define CLKID_CPU_CLK_TRACE_DIV 196208#define CLKID_CPU_CLK_TRACE 197209#define CLKID_PCIE_PLL_DCO 198210#define CLKID_PCIE_PLL_DCO_DIV2 199211#define CLKID_PCIE_PLL_OD 200212#define CLKID_PCIE_PLL 201213#define CLKID_VDEC_1_SEL 202214#define CLKID_VDEC_1_DIV 203215#define CLKID_VDEC_1 204216#define CLKID_VDEC_HEVC_SEL 205217#define CLKID_VDEC_HEVC_DIV 206218#define CLKID_VDEC_HEVC 207219#define CLKID_VDEC_HEVCF_SEL 208220#define CLKID_VDEC_HEVCF_DIV 209221#define CLKID_VDEC_HEVCF 210222#define CLKID_TS_DIV 211223#define CLKID_TS 212224#define CLKID_SYS1_PLL_DCO 213225#define CLKID_SYS1_PLL 214226#define CLKID_SYS1_PLL_DIV16_EN 215227#define CLKID_SYS1_PLL_DIV16 216228#define CLKID_CPUB_CLK_DYN0_SEL 217229#define CLKID_CPUB_CLK_DYN0_DIV 218230#define CLKID_CPUB_CLK_DYN0 219231#define CLKID_CPUB_CLK_DYN1_SEL 220232#define CLKID_CPUB_CLK_DYN1_DIV 221233#define CLKID_CPUB_CLK_DYN1 222234#define CLKID_CPUB_CLK_DYN 223235#define CLKID_CPUB_CLK 224236#define CLKID_CPUB_CLK_DIV16_EN 225237#define CLKID_CPUB_CLK_DIV16 226238#define CLKID_CPUB_CLK_DIV2 227239#define CLKID_CPUB_CLK_DIV3 228240#define CLKID_CPUB_CLK_DIV4 229241#define CLKID_CPUB_CLK_DIV5 230242#define CLKID_CPUB_CLK_DIV6 231243#define CLKID_CPUB_CLK_DIV7 232244#define CLKID_CPUB_CLK_DIV8 233245#define CLKID_CPUB_CLK_APB_SEL 234246#define CLKID_CPUB_CLK_APB 235247#define CLKID_CPUB_CLK_ATB_SEL 236248#define CLKID_CPUB_CLK_ATB 237249#define CLKID_CPUB_CLK_AXI_SEL 238250#define CLKID_CPUB_CLK_AXI 239251#define CLKID_CPUB_CLK_TRACE_SEL 240252#define CLKID_CPUB_CLK_TRACE 241253#define CLKID_GP1_PLL_DCO 242254#define CLKID_GP1_PLL 243255#define CLKID_DSU_CLK_DYN0_SEL 244256#define CLKID_DSU_CLK_DYN0_DIV 245257#define CLKID_DSU_CLK_DYN0 246258#define CLKID_DSU_CLK_DYN1_SEL 247259#define CLKID_DSU_CLK_DYN1_DIV 248260#define CLKID_DSU_CLK_DYN1 249261#define CLKID_DSU_CLK_DYN 250262#define CLKID_DSU_CLK_FINAL 251263#define CLKID_DSU_CLK 252264#define CLKID_CPU1_CLK 253265#define CLKID_CPU2_CLK 254266#define CLKID_CPU3_CLK 255267#define CLKID_SPICC0_SCLK_SEL 256268#define CLKID_SPICC0_SCLK_DIV 257269#define CLKID_SPICC0_SCLK 258270#define CLKID_SPICC1_SCLK_SEL 259271#define CLKID_SPICC1_SCLK_DIV 260272#define CLKID_SPICC1_SCLK 261273#define CLKID_NNA_AXI_CLK_SEL 262274#define CLKID_NNA_AXI_CLK_DIV 263275#define CLKID_NNA_AXI_CLK 264276#define CLKID_NNA_CORE_CLK_SEL 265277#define CLKID_NNA_CORE_CLK_DIV 266278#define CLKID_NNA_CORE_CLK 267279#define CLKID_MIPI_DSI_PXCLK_DIV 268280#define CLKID_MIPI_DSI_PXCLK_SEL 269281#define CLKID_MIPI_DSI_PXCLK 270282#define CLKID_CTS_ENCL 271283#define CLKID_CTS_ENCL_SEL 272284#define CLKID_MIPI_ISP_DIV 273285#define CLKID_MIPI_ISP_SEL 274286#define CLKID_MIPI_ISP 275287#define CLKID_MIPI_ISP_GATE 276288#define CLKID_MIPI_ISP_CSI_PHY0 277289#define CLKID_MIPI_ISP_CSI_PHY1 278290 291#endif /* __G12A_CLKC_H */292