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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * GXBB clock tree IDs4 */5 6#ifndef __GXBB_CLKC_H7#define __GXBB_CLKC_H8 9#define CLKID_SYS_PLL		010#define CLKID_HDMI_PLL		211#define CLKID_FIXED_PLL		312#define CLKID_FCLK_DIV2		413#define CLKID_FCLK_DIV3		514#define CLKID_FCLK_DIV4		615#define CLKID_FCLK_DIV5		716#define CLKID_FCLK_DIV7		817#define CLKID_GP0_PLL		918#define CLKID_MPEG_SEL		1019#define CLKID_MPEG_DIV		1120#define CLKID_CLK81		1221#define CLKID_MPLL0		1322#define CLKID_MPLL1		1423#define CLKID_MPLL2		1524#define CLKID_DDR		1625#define CLKID_DOS		1726#define CLKID_ISA		1827#define CLKID_PL301		1928#define CLKID_PERIPHS		2029#define CLKID_SPICC		2130#define CLKID_I2C		2231#define CLKID_SAR_ADC		2332#define CLKID_SMART_CARD	2433#define CLKID_RNG0		2534#define CLKID_UART0		2635#define CLKID_SDHC		2736#define CLKID_STREAM		2837#define CLKID_ASYNC_FIFO	2938#define CLKID_SDIO		3039#define CLKID_ABUF		3140#define CLKID_HIU_IFACE		3241#define CLKID_ASSIST_MISC	3342#define CLKID_SPI		3443#define CLKID_ETH		3644#define CLKID_I2S_SPDIF		3545#define CLKID_DEMUX		3746#define CLKID_AIU_GLUE		3847#define CLKID_IEC958		3948#define CLKID_I2S_OUT		4049#define CLKID_AMCLK		4150#define CLKID_AIFIFO2		4251#define CLKID_MIXER		4352#define CLKID_MIXER_IFACE	4453#define CLKID_ADC		4554#define CLKID_BLKMV		4655#define CLKID_AIU		4756#define CLKID_UART1		4857#define CLKID_G2D		4958#define CLKID_USB0		5059#define CLKID_USB1		5160#define CLKID_RESET		5261#define CLKID_NAND		5362#define CLKID_DOS_PARSER	5463#define CLKID_USB		5564#define CLKID_VDIN1		5665#define CLKID_AHB_ARB0		5766#define CLKID_EFUSE		5867#define CLKID_BOOT_ROM		5968#define CLKID_AHB_DATA_BUS	6069#define CLKID_AHB_CTRL_BUS	6170#define CLKID_HDMI_INTR_SYNC	6271#define CLKID_HDMI_PCLK		6372#define CLKID_USB1_DDR_BRIDGE	6473#define CLKID_USB0_DDR_BRIDGE	6574#define CLKID_MMC_PCLK		6675#define CLKID_DVIN		6776#define CLKID_UART2		6877#define CLKID_SANA		6978#define CLKID_VPU_INTR		7079#define CLKID_SEC_AHB_AHB3_BRIDGE 7180#define CLKID_CLK81_A53		7281#define CLKID_VCLK2_VENCI0	7382#define CLKID_VCLK2_VENCI1	7483#define CLKID_VCLK2_VENCP0	7584#define CLKID_VCLK2_VENCP1	7685#define CLKID_GCLK_VENCI_INT0	7786#define CLKID_GCLK_VENCI_INT	7887#define CLKID_DAC_CLK		7988#define CLKID_AOCLK_GATE	8089#define CLKID_IEC958_GATE	8190#define CLKID_ENC480P		8291#define CLKID_RNG1		8392#define CLKID_GCLK_VENCI_INT1	8493#define CLKID_VCLK2_VENCLMCC	8594#define CLKID_VCLK2_VENCL	8695#define CLKID_VCLK_OTHER	8796#define CLKID_EDP		8897#define CLKID_AO_MEDIA_CPU	8998#define CLKID_AO_AHB_SRAM	9099#define CLKID_AO_AHB_BUS	91100#define CLKID_AO_IFACE		92101#define CLKID_AO_I2C		93102#define CLKID_SD_EMMC_A		94103#define CLKID_SD_EMMC_B		95104#define CLKID_SD_EMMC_C		96105#define CLKID_SAR_ADC_CLK	97106#define CLKID_SAR_ADC_SEL	98107#define CLKID_SAR_ADC_DIV	99108#define CLKID_MALI_0_SEL	100109#define CLKID_MALI_0_DIV	101110#define CLKID_MALI_0		102111#define CLKID_MALI_1_SEL	103112#define CLKID_MALI_1_DIV	104113#define CLKID_MALI_1		105114#define CLKID_MALI		106115#define CLKID_CTS_AMCLK		107116#define CLKID_CTS_AMCLK_SEL	108117#define CLKID_CTS_AMCLK_DIV	109118#define CLKID_CTS_MCLK_I958	110119#define CLKID_CTS_MCLK_I958_SEL	111120#define CLKID_CTS_MCLK_I958_DIV 112121#define CLKID_CTS_I958		113122#define CLKID_32K_CLK		114123#define CLKID_32K_CLK_SEL	115124#define CLKID_32K_CLK_DIV	116125#define CLKID_SD_EMMC_A_CLK0_SEL 117126#define CLKID_SD_EMMC_A_CLK0_DIV 118127#define CLKID_SD_EMMC_A_CLK0	119128#define CLKID_SD_EMMC_B_CLK0_SEL 120129#define CLKID_SD_EMMC_B_CLK0_DIV 121130#define CLKID_SD_EMMC_B_CLK0	122131#define CLKID_SD_EMMC_C_CLK0_SEL 123132#define CLKID_SD_EMMC_C_CLK0_DIV 124133#define CLKID_SD_EMMC_C_CLK0	125134#define CLKID_VPU_0_SEL		126135#define CLKID_VPU_0_DIV		127136#define CLKID_VPU_0		128137#define CLKID_VPU_1_SEL		129138#define CLKID_VPU_1_DIV		130139#define CLKID_VPU_1		131140#define CLKID_VPU		132141#define CLKID_VAPB_0_SEL	133142#define CLKID_VAPB_0_DIV	134143#define CLKID_VAPB_0		135144#define CLKID_VAPB_1_SEL	136145#define CLKID_VAPB_1_DIV	137146#define CLKID_VAPB_1		138147#define CLKID_VAPB_SEL		139148#define CLKID_VAPB		140149#define CLKID_HDMI_PLL_PRE_MULT	141150#define CLKID_MPLL0_DIV		142151#define CLKID_MPLL1_DIV		143152#define CLKID_MPLL2_DIV		144153#define CLKID_MPLL_PREDIV	145154#define CLKID_FCLK_DIV2_DIV	146155#define CLKID_FCLK_DIV3_DIV	147156#define CLKID_FCLK_DIV4_DIV	148157#define CLKID_FCLK_DIV5_DIV	149158#define CLKID_FCLK_DIV7_DIV	150159#define CLKID_VDEC_1_SEL	151160#define CLKID_VDEC_1_DIV	152161#define CLKID_VDEC_1		153162#define CLKID_VDEC_HEVC_SEL	154163#define CLKID_VDEC_HEVC_DIV	155164#define CLKID_VDEC_HEVC		156165#define CLKID_GEN_CLK_SEL	157166#define CLKID_GEN_CLK_DIV	158167#define CLKID_GEN_CLK		159168#define CLKID_FIXED_PLL_DCO	160169#define CLKID_HDMI_PLL_DCO	161170#define CLKID_HDMI_PLL_OD	162171#define CLKID_HDMI_PLL_OD2	163172#define CLKID_SYS_PLL_DCO	164173#define CLKID_GP0_PLL_DCO	165174#define CLKID_VID_PLL		166175#define CLKID_VID_PLL_SEL	167176#define CLKID_VID_PLL_DIV	168177#define CLKID_VCLK_SEL		169178#define CLKID_VCLK2_SEL		170179#define CLKID_VCLK_INPUT	171180#define CLKID_VCLK2_INPUT	172181#define CLKID_VCLK_DIV		173182#define CLKID_VCLK2_DIV		174183#define CLKID_VCLK		175184#define CLKID_VCLK2		176185#define CLKID_VCLK_DIV2_EN	177186#define CLKID_VCLK_DIV4_EN	178187#define CLKID_VCLK_DIV6_EN	179188#define CLKID_VCLK_DIV12_EN	180189#define CLKID_VCLK2_DIV2_EN	181190#define CLKID_VCLK2_DIV4_EN	182191#define CLKID_VCLK2_DIV6_EN	183192#define CLKID_VCLK2_DIV12_EN	184193#define CLKID_VCLK_DIV1		185194#define CLKID_VCLK_DIV2		186195#define CLKID_VCLK_DIV4		187196#define CLKID_VCLK_DIV6		188197#define CLKID_VCLK_DIV12	189198#define CLKID_VCLK2_DIV1	190199#define CLKID_VCLK2_DIV2	191200#define CLKID_VCLK2_DIV4	192201#define CLKID_VCLK2_DIV6	193202#define CLKID_VCLK2_DIV12	194203#define CLKID_CTS_ENCI_SEL	195204#define CLKID_CTS_ENCP_SEL	196205#define CLKID_CTS_VDAC_SEL	197206#define CLKID_HDMI_TX_SEL	198207#define CLKID_CTS_ENCI		199208#define CLKID_CTS_ENCP		200209#define CLKID_CTS_VDAC		201210#define CLKID_HDMI_TX		202211#define CLKID_HDMI_SEL		203212#define CLKID_HDMI_DIV		204213#define CLKID_HDMI		205214#define CLKID_ACODEC		206215 216#endif /* __GXBB_CLKC_H */217