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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.4 */5 6#ifndef __DTS_HI3516CV300_CLOCK_H7#define __DTS_HI3516CV300_CLOCK_H8 9/* hi3516CV300 core CRG */10#define HI3516CV300_APB_CLK 011#define HI3516CV300_UART0_CLK 112#define HI3516CV300_UART1_CLK 213#define HI3516CV300_UART2_CLK 314#define HI3516CV300_SPI0_CLK 415#define HI3516CV300_SPI1_CLK 516#define HI3516CV300_FMC_CLK 617#define HI3516CV300_MMC0_CLK 718#define HI3516CV300_MMC1_CLK 819#define HI3516CV300_MMC2_CLK 920#define HI3516CV300_MMC3_CLK 1021#define HI3516CV300_ETH_CLK 1122#define HI3516CV300_ETH_MACIF_CLK 1223#define HI3516CV300_DMAC_CLK 1324#define HI3516CV300_PWM_CLK 1425#define HI3516CV300_USB2_BUS_CLK 1526#define HI3516CV300_USB2_OHCI48M_CLK 1627#define HI3516CV300_USB2_OHCI12M_CLK 1728#define HI3516CV300_USB2_OTG_UTMI_CLK 1829#define HI3516CV300_USB2_HST_PHY_CLK 1930#define HI3516CV300_USB2_UTMI0_CLK 2031#define HI3516CV300_USB2_PHY_CLK 2132 33/* hi3516CV300 sysctrl CRG */34#define HI3516CV300_WDT_CLK 135 36#endif /* __DTS_HI3516CV300_CLOCK_H */37