166 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */2/*3 * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd.4 *5 * Author: Dongjiu Geng <gengdongjiu@huawei.com>6 */7 8#ifndef __DTS_HI3559AV100_CLOCK_H9#define __DTS_HI3559AV100_CLOCK_H10 11/* fixed rate */12#define HI3559AV100_FIXED_1188M 113#define HI3559AV100_FIXED_1000M 214#define HI3559AV100_FIXED_842M 315#define HI3559AV100_FIXED_792M 416#define HI3559AV100_FIXED_750M 517#define HI3559AV100_FIXED_710M 618#define HI3559AV100_FIXED_680M 719#define HI3559AV100_FIXED_667M 820#define HI3559AV100_FIXED_631M 921#define HI3559AV100_FIXED_600M 1022#define HI3559AV100_FIXED_568M 1123#define HI3559AV100_FIXED_500M 1224#define HI3559AV100_FIXED_475M 1325#define HI3559AV100_FIXED_428M 1426#define HI3559AV100_FIXED_400M 1527#define HI3559AV100_FIXED_396M 1628#define HI3559AV100_FIXED_300M 1729#define HI3559AV100_FIXED_250M 1830#define HI3559AV100_FIXED_198M 1931#define HI3559AV100_FIXED_187p5M 2032#define HI3559AV100_FIXED_150M 2133#define HI3559AV100_FIXED_148p5M 2234#define HI3559AV100_FIXED_125M 2335#define HI3559AV100_FIXED_107M 2436#define HI3559AV100_FIXED_100M 2537#define HI3559AV100_FIXED_99M 2638#define HI3559AV100_FIXED_74p25M 2739#define HI3559AV100_FIXED_72M 2840#define HI3559AV100_FIXED_60M 2941#define HI3559AV100_FIXED_54M 3042#define HI3559AV100_FIXED_50M 3143#define HI3559AV100_FIXED_49p5M 3244#define HI3559AV100_FIXED_37p125M 3345#define HI3559AV100_FIXED_36M 3446#define HI3559AV100_FIXED_32p4M 3547#define HI3559AV100_FIXED_27M 3648#define HI3559AV100_FIXED_25M 3749#define HI3559AV100_FIXED_24M 3850#define HI3559AV100_FIXED_12M 3951#define HI3559AV100_FIXED_3M 4052#define HI3559AV100_FIXED_1p6M 4153#define HI3559AV100_FIXED_400K 4254#define HI3559AV100_FIXED_100K 4355#define HI3559AV100_FIXED_200M 4456#define HI3559AV100_FIXED_75M 7557 58#define HI3559AV100_I2C0_CLK 5059#define HI3559AV100_I2C1_CLK 5160#define HI3559AV100_I2C2_CLK 5261#define HI3559AV100_I2C3_CLK 5362#define HI3559AV100_I2C4_CLK 5463#define HI3559AV100_I2C5_CLK 5564#define HI3559AV100_I2C6_CLK 5665#define HI3559AV100_I2C7_CLK 5766#define HI3559AV100_I2C8_CLK 5867#define HI3559AV100_I2C9_CLK 5968#define HI3559AV100_I2C10_CLK 6069#define HI3559AV100_I2C11_CLK 6170 71#define HI3559AV100_SPI0_CLK 6272#define HI3559AV100_SPI1_CLK 6373#define HI3559AV100_SPI2_CLK 6474#define HI3559AV100_SPI3_CLK 6575#define HI3559AV100_SPI4_CLK 6676#define HI3559AV100_SPI5_CLK 6777#define HI3559AV100_SPI6_CLK 6878 79#define HI3559AV100_EDMAC_CLK 6980#define HI3559AV100_EDMAC_AXICLK 7081#define HI3559AV100_EDMAC1_CLK 7182#define HI3559AV100_EDMAC1_AXICLK 7283#define HI3559AV100_VDMAC_CLK 7384 85/* mux clocks */86#define HI3559AV100_FMC_MUX 8087#define HI3559AV100_SYSAPB_MUX 8188#define HI3559AV100_UART_MUX 8289#define HI3559AV100_SYSBUS_MUX 8390#define HI3559AV100_A73_MUX 8491#define HI3559AV100_MMC0_MUX 8592#define HI3559AV100_MMC1_MUX 8693#define HI3559AV100_MMC2_MUX 8794#define HI3559AV100_MMC3_MUX 8895 96/* gate clocks */97#define HI3559AV100_FMC_CLK 9098#define HI3559AV100_UART0_CLK 9199#define HI3559AV100_UART1_CLK 92100#define HI3559AV100_UART2_CLK 93101#define HI3559AV100_UART3_CLK 94102#define HI3559AV100_UART4_CLK 95103#define HI3559AV100_MMC0_CLK 96104#define HI3559AV100_MMC1_CLK 97105#define HI3559AV100_MMC2_CLK 98106#define HI3559AV100_MMC3_CLK 99107 108#define HI3559AV100_ETH_CLK 100109#define HI3559AV100_ETH_MACIF_CLK 101110#define HI3559AV100_ETH1_CLK 102111#define HI3559AV100_ETH1_MACIF_CLK 103112 113/* complex */114#define HI3559AV100_MAC0_CLK 110115#define HI3559AV100_MAC1_CLK 111116#define HI3559AV100_SATA_CLK 112117#define HI3559AV100_USB_CLK 113118#define HI3559AV100_USB1_CLK 114119 120/* pll clocks */121#define HI3559AV100_APLL_CLK 250122#define HI3559AV100_GPLL_CLK 251123 124#define HI3559AV100_CRG_NR_CLKS 256125 126#define HI3559AV100_SHUB_SOURCE_SOC_24M 0127#define HI3559AV100_SHUB_SOURCE_SOC_200M 1128#define HI3559AV100_SHUB_SOURCE_SOC_300M 2129#define HI3559AV100_SHUB_SOURCE_PLL 3130#define HI3559AV100_SHUB_SOURCE_CLK 4131 132#define HI3559AV100_SHUB_I2C0_CLK 10133#define HI3559AV100_SHUB_I2C1_CLK 11134#define HI3559AV100_SHUB_I2C2_CLK 12135#define HI3559AV100_SHUB_I2C3_CLK 13136#define HI3559AV100_SHUB_I2C4_CLK 14137#define HI3559AV100_SHUB_I2C5_CLK 15138#define HI3559AV100_SHUB_I2C6_CLK 16139#define HI3559AV100_SHUB_I2C7_CLK 17140 141#define HI3559AV100_SHUB_SPI_SOURCE_CLK 20142#define HI3559AV100_SHUB_SPI4_SOURCE_CLK 21143#define HI3559AV100_SHUB_SPI0_CLK 22144#define HI3559AV100_SHUB_SPI1_CLK 23145#define HI3559AV100_SHUB_SPI2_CLK 24146#define HI3559AV100_SHUB_SPI3_CLK 25147#define HI3559AV100_SHUB_SPI4_CLK 26148 149#define HI3559AV100_SHUB_UART_CLK_32K 30150#define HI3559AV100_SHUB_UART_SOURCE_CLK 31151#define HI3559AV100_SHUB_UART_DIV_CLK 32152#define HI3559AV100_SHUB_UART0_CLK 33153#define HI3559AV100_SHUB_UART1_CLK 34154#define HI3559AV100_SHUB_UART2_CLK 35155#define HI3559AV100_SHUB_UART3_CLK 36156#define HI3559AV100_SHUB_UART4_CLK 37157#define HI3559AV100_SHUB_UART5_CLK 38158#define HI3559AV100_SHUB_UART6_CLK 39159 160#define HI3559AV100_SHUB_EDMAC_CLK 40161 162#define HI3559AV100_SHUB_NR_CLKS 50163 164#endif /* __DTS_HI3559AV100_CLOCK_H */165 166