144 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2012-2013 Hisilicon Limited.4 * Copyright (c) 2012-2013 Linaro Limited.5 *6 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>7 * Xin Li <li.xin@linaro.org>8 */9 10#ifndef __DTS_HI3620_CLOCK_H11#define __DTS_HI3620_CLOCK_H12 13#define HI3620_NONE_CLOCK 014 15/* fixed rate & fixed factor clocks */16#define HI3620_OSC32K 117#define HI3620_OSC26M 218#define HI3620_PCLK 319#define HI3620_PLL_ARM0 420#define HI3620_PLL_ARM1 521#define HI3620_PLL_PERI 622#define HI3620_PLL_USB 723#define HI3620_PLL_HDMI 824#define HI3620_PLL_GPU 925#define HI3620_RCLK_TCXO 1026#define HI3620_RCLK_CFGAXI 1127#define HI3620_RCLK_PICO 1228 29/* mux clocks */30#define HI3620_TIMER0_MUX 3231#define HI3620_TIMER1_MUX 3332#define HI3620_TIMER2_MUX 3433#define HI3620_TIMER3_MUX 3534#define HI3620_TIMER4_MUX 3635#define HI3620_TIMER5_MUX 3736#define HI3620_TIMER6_MUX 3837#define HI3620_TIMER7_MUX 3938#define HI3620_TIMER8_MUX 4039#define HI3620_TIMER9_MUX 4140#define HI3620_UART0_MUX 4241#define HI3620_UART1_MUX 4342#define HI3620_UART2_MUX 4443#define HI3620_UART3_MUX 4544#define HI3620_UART4_MUX 4645#define HI3620_SPI0_MUX 4746#define HI3620_SPI1_MUX 4847#define HI3620_SPI2_MUX 4948#define HI3620_SAXI_MUX 5049#define HI3620_PWM0_MUX 5150#define HI3620_PWM1_MUX 5251#define HI3620_SD_MUX 5352#define HI3620_MMC1_MUX 5453#define HI3620_MMC1_MUX2 5554#define HI3620_G2D_MUX 5655#define HI3620_VENC_MUX 5756#define HI3620_VDEC_MUX 5857#define HI3620_VPP_MUX 5958#define HI3620_EDC0_MUX 6059#define HI3620_LDI0_MUX 6160#define HI3620_EDC1_MUX 6261#define HI3620_LDI1_MUX 6362#define HI3620_RCLK_HSIC 6463#define HI3620_MMC2_MUX 6564#define HI3620_MMC3_MUX 6665 66/* divider clocks */67#define HI3620_SHAREAXI_DIV 12868#define HI3620_CFGAXI_DIV 12969#define HI3620_SD_DIV 13070#define HI3620_MMC1_DIV 13171#define HI3620_HSIC_DIV 13272#define HI3620_MMC2_DIV 13373#define HI3620_MMC3_DIV 13474 75/* gate clocks */76#define HI3620_TIMERCLK01 16077#define HI3620_TIMER_RCLK01 16178#define HI3620_TIMERCLK23 16279#define HI3620_TIMER_RCLK23 16380#define HI3620_TIMERCLK45 16481#define HI3620_TIMERCLK67 16582#define HI3620_TIMERCLK89 16683#define HI3620_RTCCLK 16784#define HI3620_KPC_CLK 16885#define HI3620_GPIOCLK0 16986#define HI3620_GPIOCLK1 17087#define HI3620_GPIOCLK2 17188#define HI3620_GPIOCLK3 17289#define HI3620_GPIOCLK4 17390#define HI3620_GPIOCLK5 17491#define HI3620_GPIOCLK6 17592#define HI3620_GPIOCLK7 17693#define HI3620_GPIOCLK8 17794#define HI3620_GPIOCLK9 17895#define HI3620_GPIOCLK10 17996#define HI3620_GPIOCLK11 18097#define HI3620_GPIOCLK12 18198#define HI3620_GPIOCLK13 18299#define HI3620_GPIOCLK14 183100#define HI3620_GPIOCLK15 184101#define HI3620_GPIOCLK16 185102#define HI3620_GPIOCLK17 186103#define HI3620_GPIOCLK18 187104#define HI3620_GPIOCLK19 188105#define HI3620_GPIOCLK20 189106#define HI3620_GPIOCLK21 190107#define HI3620_DPHY0_CLK 191108#define HI3620_DPHY1_CLK 192109#define HI3620_DPHY2_CLK 193110#define HI3620_USBPHY_CLK 194111#define HI3620_ACP_CLK 195112#define HI3620_PWMCLK0 196113#define HI3620_PWMCLK1 197114#define HI3620_UARTCLK0 198115#define HI3620_UARTCLK1 199116#define HI3620_UARTCLK2 200117#define HI3620_UARTCLK3 201118#define HI3620_UARTCLK4 202119#define HI3620_SPICLK0 203120#define HI3620_SPICLK1 204121#define HI3620_SPICLK2 205122#define HI3620_I2CCLK0 206123#define HI3620_I2CCLK1 207124#define HI3620_I2CCLK2 208125#define HI3620_I2CCLK3 209126#define HI3620_SCI_CLK 210127#define HI3620_DDRC_PER_CLK 211128#define HI3620_DMAC_CLK 212129#define HI3620_USB2DVC_CLK 213130#define HI3620_SD_CLK 214131#define HI3620_MMC_CLK1 215132#define HI3620_MMC_CLK2 216133#define HI3620_MMC_CLK3 217134#define HI3620_MCU_CLK 218135 136#define HI3620_SD_CIUCLK 0137#define HI3620_MMC_CIUCLK1 1138#define HI3620_MMC_CIUCLK2 2139#define HI3620_MMC_CIUCLK3 3140 141#define HI3620_NR_CLKS 219142 143#endif /* __DTS_HI3620_CLOCK_H */144