215 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2016-2017 Linaro Ltd.4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.5 */6 7#ifndef __DTS_HI3660_CLOCK_H8#define __DTS_HI3660_CLOCK_H9 10/* fixed rate clocks */11#define HI3660_CLKIN_SYS 012#define HI3660_CLKIN_REF 113#define HI3660_CLK_FLL_SRC 214#define HI3660_CLK_PPLL0 315#define HI3660_CLK_PPLL1 416#define HI3660_CLK_PPLL2 517#define HI3660_CLK_PPLL3 618#define HI3660_CLK_SCPLL 719#define HI3660_PCLK 820#define HI3660_CLK_UART0_DBG 921#define HI3660_CLK_UART6 1022#define HI3660_OSC32K 1123#define HI3660_OSC19M 1224#define HI3660_CLK_480M 1325#define HI3660_CLK_INV 1426 27/* clk in crgctrl */28#define HI3660_FACTOR_UART3 1529#define HI3660_CLK_FACTOR_MMC 1630#define HI3660_CLK_GATE_I2C0 1731#define HI3660_CLK_GATE_I2C1 1832#define HI3660_CLK_GATE_I2C2 1933#define HI3660_CLK_GATE_I2C6 2034#define HI3660_CLK_DIV_SYSBUS 2135#define HI3660_CLK_DIV_320M 2236#define HI3660_CLK_DIV_A53 2337#define HI3660_CLK_GATE_SPI0 2438#define HI3660_CLK_GATE_SPI2 2539#define HI3660_PCIEPHY_REF 2640#define HI3660_CLK_ABB_USB 2741#define HI3660_HCLK_GATE_SDIO0 2842#define HI3660_HCLK_GATE_SD 2943#define HI3660_CLK_GATE_AOMM 3044#define HI3660_PCLK_GPIO0 3145#define HI3660_PCLK_GPIO1 3246#define HI3660_PCLK_GPIO2 3347#define HI3660_PCLK_GPIO3 3448#define HI3660_PCLK_GPIO4 3549#define HI3660_PCLK_GPIO5 3650#define HI3660_PCLK_GPIO6 3751#define HI3660_PCLK_GPIO7 3852#define HI3660_PCLK_GPIO8 3953#define HI3660_PCLK_GPIO9 4054#define HI3660_PCLK_GPIO10 4155#define HI3660_PCLK_GPIO11 4256#define HI3660_PCLK_GPIO12 4357#define HI3660_PCLK_GPIO13 4458#define HI3660_PCLK_GPIO14 4559#define HI3660_PCLK_GPIO15 4660#define HI3660_PCLK_GPIO16 4761#define HI3660_PCLK_GPIO17 4862#define HI3660_PCLK_GPIO18 4963#define HI3660_PCLK_GPIO19 5064#define HI3660_PCLK_GPIO20 5165#define HI3660_PCLK_GPIO21 5266#define HI3660_CLK_GATE_SPI3 5367#define HI3660_CLK_GATE_I2C7 5468#define HI3660_CLK_GATE_I2C3 5569#define HI3660_CLK_GATE_SPI1 5670#define HI3660_CLK_GATE_UART1 5771#define HI3660_CLK_GATE_UART2 5872#define HI3660_CLK_GATE_UART4 5973#define HI3660_CLK_GATE_UART5 6074#define HI3660_CLK_GATE_I2C4 6175#define HI3660_CLK_GATE_DMAC 6276#define HI3660_PCLK_GATE_DSS 6377#define HI3660_ACLK_GATE_DSS 6478#define HI3660_CLK_GATE_LDI1 6579#define HI3660_CLK_GATE_LDI0 6680#define HI3660_CLK_GATE_VIVOBUS 6781#define HI3660_CLK_GATE_EDC0 6882#define HI3660_CLK_GATE_TXDPHY0_CFG 6983#define HI3660_CLK_GATE_TXDPHY0_REF 7084#define HI3660_CLK_GATE_TXDPHY1_CFG 7185#define HI3660_CLK_GATE_TXDPHY1_REF 7286#define HI3660_ACLK_GATE_USB3OTG 7387#define HI3660_CLK_GATE_SPI4 7488#define HI3660_CLK_GATE_SD 7589#define HI3660_CLK_GATE_SDIO0 7690#define HI3660_CLK_GATE_UFS_SUBSYS 7791#define HI3660_PCLK_GATE_DSI0 7892#define HI3660_PCLK_GATE_DSI1 7993#define HI3660_ACLK_GATE_PCIE 8094#define HI3660_PCLK_GATE_PCIE_SYS 8195#define HI3660_CLK_GATE_PCIEAUX 8296#define HI3660_PCLK_GATE_PCIE_PHY 8397#define HI3660_CLK_ANDGT_LDI0 8498#define HI3660_CLK_ANDGT_LDI1 8599#define HI3660_CLK_ANDGT_EDC0 86100#define HI3660_CLK_GATE_UFSPHY_GT 87101#define HI3660_CLK_ANDGT_MMC 88102#define HI3660_CLK_ANDGT_SD 89103#define HI3660_CLK_A53HPM_ANDGT 90104#define HI3660_CLK_ANDGT_SDIO 91105#define HI3660_CLK_ANDGT_UART0 92106#define HI3660_CLK_ANDGT_UART1 93107#define HI3660_CLK_ANDGT_UARTH 94108#define HI3660_CLK_ANDGT_SPI 95109#define HI3660_CLK_VIVOBUS_ANDGT 96110#define HI3660_CLK_AOMM_ANDGT 97111#define HI3660_CLK_320M_PLL_GT 98112#define HI3660_AUTODIV_EMMC0BUS 99113#define HI3660_AUTODIV_SYSBUS 100114#define HI3660_CLK_GATE_UFSPHY_CFG 101115#define HI3660_CLK_GATE_UFSIO_REF 102116#define HI3660_CLK_MUX_SYSBUS 103117#define HI3660_CLK_MUX_UART0 104118#define HI3660_CLK_MUX_UART1 105119#define HI3660_CLK_MUX_UARTH 106120#define HI3660_CLK_MUX_SPI 107121#define HI3660_CLK_MUX_I2C 108122#define HI3660_CLK_MUX_MMC_PLL 109123#define HI3660_CLK_MUX_LDI1 110124#define HI3660_CLK_MUX_LDI0 111125#define HI3660_CLK_MUX_SD_PLL 112126#define HI3660_CLK_MUX_SD_SYS 113127#define HI3660_CLK_MUX_EDC0 114128#define HI3660_CLK_MUX_SDIO_SYS 115129#define HI3660_CLK_MUX_SDIO_PLL 116130#define HI3660_CLK_MUX_VIVOBUS 117131#define HI3660_CLK_MUX_A53HPM 118132#define HI3660_CLK_MUX_320M 119133#define HI3660_CLK_MUX_IOPERI 120134#define HI3660_CLK_DIV_UART0 121135#define HI3660_CLK_DIV_UART1 122136#define HI3660_CLK_DIV_UARTH 123137#define HI3660_CLK_DIV_MMC 124138#define HI3660_CLK_DIV_SD 125139#define HI3660_CLK_DIV_EDC0 126140#define HI3660_CLK_DIV_LDI0 127141#define HI3660_CLK_DIV_SDIO 128142#define HI3660_CLK_DIV_LDI1 129143#define HI3660_CLK_DIV_SPI 130144#define HI3660_CLK_DIV_VIVOBUS 131145#define HI3660_CLK_DIV_I2C 132146#define HI3660_CLK_DIV_UFSPHY 133147#define HI3660_CLK_DIV_CFGBUS 134148#define HI3660_CLK_DIV_MMC0BUS 135149#define HI3660_CLK_DIV_MMC1BUS 136150#define HI3660_CLK_DIV_UFSPERI 137151#define HI3660_CLK_DIV_AOMM 138152#define HI3660_CLK_DIV_IOPERI 139153#define HI3660_VENC_VOLT_HOLD 140154#define HI3660_PERI_VOLT_HOLD 141155#define HI3660_CLK_GATE_VENC 142156#define HI3660_CLK_GATE_VDEC 143157#define HI3660_CLK_ANDGT_VENC 144158#define HI3660_CLK_ANDGT_VDEC 145159#define HI3660_CLK_MUX_VENC 146160#define HI3660_CLK_MUX_VDEC 147161#define HI3660_CLK_DIV_VENC 148162#define HI3660_CLK_DIV_VDEC 149163#define HI3660_CLK_FAC_ISP_SNCLK 150164#define HI3660_CLK_GATE_ISP_SNCLK0 151165#define HI3660_CLK_GATE_ISP_SNCLK1 152166#define HI3660_CLK_GATE_ISP_SNCLK2 153167#define HI3660_CLK_ANGT_ISP_SNCLK 154168#define HI3660_CLK_MUX_ISP_SNCLK 155169#define HI3660_CLK_DIV_ISP_SNCLK 156170 171/* clk in pmuctrl */172#define HI3660_GATE_ABB_192 0173 174/* clk in pctrl */175#define HI3660_GATE_UFS_TCXO_EN 0176#define HI3660_GATE_USB_TCXO_EN 1177 178/* clk in sctrl */179#define HI3660_PCLK_AO_GPIO0 0180#define HI3660_PCLK_AO_GPIO1 1181#define HI3660_PCLK_AO_GPIO2 2182#define HI3660_PCLK_AO_GPIO3 3183#define HI3660_PCLK_AO_GPIO4 4184#define HI3660_PCLK_AO_GPIO5 5185#define HI3660_PCLK_AO_GPIO6 6186#define HI3660_PCLK_GATE_MMBUF 7187#define HI3660_CLK_GATE_DSS_AXI_MM 8188#define HI3660_PCLK_MMBUF_ANDGT 9189#define HI3660_CLK_MMBUF_PLL_ANDGT 10190#define HI3660_CLK_FLL_MMBUF_ANDGT 11191#define HI3660_CLK_SYS_MMBUF_ANDGT 12192#define HI3660_CLK_GATE_PCIEPHY_GT 13193#define HI3660_ACLK_MUX_MMBUF 14194#define HI3660_CLK_SW_MMBUF 15195#define HI3660_CLK_DIV_AOBUS 16196#define HI3660_PCLK_DIV_MMBUF 17197#define HI3660_ACLK_DIV_MMBUF 18198#define HI3660_CLK_DIV_PCIEPHY 19199 200/* clk in iomcu */201#define HI3660_CLK_I2C0_IOMCU 0202#define HI3660_CLK_I2C1_IOMCU 1203#define HI3660_CLK_I2C2_IOMCU 2204#define HI3660_CLK_I2C6_IOMCU 3205#define HI3660_CLK_IOMCU_PERI0 4206 207/* clk in stub clock */208#define HI3660_CLK_STUB_CLUSTER0 0209#define HI3660_CLK_STUB_CLUSTER1 1210#define HI3660_CLK_STUB_GPU 2211#define HI3660_CLK_STUB_DDR 3212#define HI3660_CLK_STUB_NUM 4213 214#endif /* __DTS_HI3660_CLOCK_H */215