349 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Device Tree binding constants for HiSilicon Hi3670 SoC4 *5 * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.6 * Copyright (c) 2018 Linaro Ltd.7 */8 9#ifndef __DT_BINDINGS_CLOCK_HI3670_H10#define __DT_BINDINGS_CLOCK_HI3670_H11 12/* clk in stub clock */13#define HI3670_CLK_STUB_CLUSTER0 014#define HI3670_CLK_STUB_CLUSTER1 115#define HI3670_CLK_STUB_GPU 216#define HI3670_CLK_STUB_DDR 317#define HI3670_CLK_STUB_DDR_VOTE 418#define HI3670_CLK_STUB_DDR_LIMIT 519#define HI3670_CLK_STUB_NUM 620 21/* clk in crg clock */22#define HI3670_CLKIN_SYS 023#define HI3670_CLKIN_REF 124#define HI3670_CLK_FLL_SRC 225#define HI3670_CLK_PPLL0 326#define HI3670_CLK_PPLL1 427#define HI3670_CLK_PPLL2 528#define HI3670_CLK_PPLL3 629#define HI3670_CLK_PPLL4 730#define HI3670_CLK_PPLL6 831#define HI3670_CLK_PPLL7 932#define HI3670_CLK_PPLL_PCIE 1033#define HI3670_CLK_PCIEPLL_REV 1134#define HI3670_CLK_SCPLL 1235#define HI3670_PCLK 1336#define HI3670_CLK_UART0_DBG 1437#define HI3670_CLK_UART6 1538#define HI3670_OSC32K 1639#define HI3670_OSC19M 1740#define HI3670_CLK_480M 1841#define HI3670_CLK_INVALID 1942#define HI3670_CLK_DIV_SYSBUS 2043#define HI3670_CLK_FACTOR_MMC 2144#define HI3670_CLK_SD_SYS 2245#define HI3670_CLK_SDIO_SYS 2346#define HI3670_CLK_DIV_A53HPM 2447#define HI3670_CLK_DIV_320M 2548#define HI3670_PCLK_GATE_UART0 2649#define HI3670_CLK_FACTOR_UART0 2750#define HI3670_CLK_FACTOR_USB3PHY_PLL 2851#define HI3670_CLK_GATE_ABB_USB 2952#define HI3670_CLK_GATE_UFSPHY_REF 3053#define HI3670_ICS_VOLT_HIGH 3154#define HI3670_ICS_VOLT_MIDDLE 3255#define HI3670_VENC_VOLT_HOLD 3356#define HI3670_VDEC_VOLT_HOLD 3457#define HI3670_EDC_VOLT_HOLD 3558#define HI3670_CLK_ISP_SNCLK_FAC 3659#define HI3670_CLK_FACTOR_RXDPHY 3760#define HI3670_AUTODIV_SYSBUS 3861#define HI3670_AUTODIV_EMMC0BUS 3962#define HI3670_PCLK_ANDGT_MMC1_PCIE 4063#define HI3670_CLK_GATE_VCODECBUS_GT 4164#define HI3670_CLK_ANDGT_SD 4265#define HI3670_CLK_SD_SYS_GT 4366#define HI3670_CLK_ANDGT_SDIO 4467#define HI3670_CLK_SDIO_SYS_GT 4568#define HI3670_CLK_A53HPM_ANDGT 4669#define HI3670_CLK_320M_PLL_GT 4770#define HI3670_CLK_ANDGT_UARTH 4871#define HI3670_CLK_ANDGT_UARTL 4972#define HI3670_CLK_ANDGT_UART0 5073#define HI3670_CLK_ANDGT_SPI 5174#define HI3670_CLK_ANDGT_PCIEAXI 5275#define HI3670_CLK_DIV_AO_ASP_GT 5376#define HI3670_CLK_GATE_CSI_TRANS 5477#define HI3670_CLK_GATE_DSI_TRANS 5578#define HI3670_CLK_ANDGT_PTP 5679#define HI3670_CLK_ANDGT_OUT0 5780#define HI3670_CLK_ANDGT_OUT1 5881#define HI3670_CLKGT_DP_AUDIO_PLL_AO 5982#define HI3670_CLK_ANDGT_VDEC 6083#define HI3670_CLK_ANDGT_VENC 6184#define HI3670_CLK_ISP_SNCLK_ANGT 6285#define HI3670_CLK_ANDGT_RXDPHY 6386#define HI3670_CLK_ANDGT_ICS 6487#define HI3670_AUTODIV_DMABUS 6588#define HI3670_CLK_MUX_SYSBUS 6689#define HI3670_CLK_MUX_VCODECBUS 6790#define HI3670_CLK_MUX_SD_SYS 6891#define HI3670_CLK_MUX_SD_PLL 6992#define HI3670_CLK_MUX_SDIO_SYS 7093#define HI3670_CLK_MUX_SDIO_PLL 7194#define HI3670_CLK_MUX_A53HPM 7295#define HI3670_CLK_MUX_320M 7396#define HI3670_CLK_MUX_UARTH 7497#define HI3670_CLK_MUX_UARTL 7598#define HI3670_CLK_MUX_UART0 7699#define HI3670_CLK_MUX_I2C 77100#define HI3670_CLK_MUX_SPI 78101#define HI3670_CLK_MUX_PCIEAXI 79102#define HI3670_CLK_MUX_AO_ASP 80103#define HI3670_CLK_MUX_VDEC 81104#define HI3670_CLK_MUX_VENC 82105#define HI3670_CLK_ISP_SNCLK_MUX0 83106#define HI3670_CLK_ISP_SNCLK_MUX1 84107#define HI3670_CLK_ISP_SNCLK_MUX2 85108#define HI3670_CLK_MUX_RXDPHY_CFG 86109#define HI3670_CLK_MUX_ICS 87110#define HI3670_CLK_DIV_CFGBUS 88111#define HI3670_CLK_DIV_MMC0BUS 89112#define HI3670_CLK_DIV_MMC1BUS 90113#define HI3670_PCLK_DIV_MMC1_PCIE 91114#define HI3670_CLK_DIV_VCODECBUS 92115#define HI3670_CLK_DIV_SD 93116#define HI3670_CLK_DIV_SDIO 94117#define HI3670_CLK_DIV_UARTH 95118#define HI3670_CLK_DIV_UARTL 96119#define HI3670_CLK_DIV_UART0 97120#define HI3670_CLK_DIV_I2C 98121#define HI3670_CLK_DIV_SPI 99122#define HI3670_CLK_DIV_PCIEAXI 100123#define HI3670_CLK_DIV_AO_ASP 101124#define HI3670_CLK_DIV_CSI_TRANS 102125#define HI3670_CLK_DIV_DSI_TRANS 103126#define HI3670_CLK_DIV_PTP 104127#define HI3670_CLK_DIV_CLKOUT0_PLL 105128#define HI3670_CLK_DIV_CLKOUT1_PLL 106129#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107130#define HI3670_CLK_DIV_VDEC 108131#define HI3670_CLK_DIV_VENC 109132#define HI3670_CLK_ISP_SNCLK_DIV0 110133#define HI3670_CLK_ISP_SNCLK_DIV1 111134#define HI3670_CLK_ISP_SNCLK_DIV2 112135#define HI3670_CLK_DIV_ICS 113136#define HI3670_PPLL1_EN_ACPU 114137#define HI3670_PPLL2_EN_ACPU 115138#define HI3670_PPLL3_EN_ACPU 116139#define HI3670_PPLL1_GT_CPU 117140#define HI3670_PPLL2_GT_CPU 118141#define HI3670_PPLL3_GT_CPU 119142#define HI3670_CLK_GATE_PPLL2_MEDIA 120143#define HI3670_CLK_GATE_PPLL3_MEDIA 121144#define HI3670_CLK_GATE_PPLL4_MEDIA 122145#define HI3670_CLK_GATE_PPLL6_MEDIA 123146#define HI3670_CLK_GATE_PPLL7_MEDIA 124147#define HI3670_PCLK_GPIO0 125148#define HI3670_PCLK_GPIO1 126149#define HI3670_PCLK_GPIO2 127150#define HI3670_PCLK_GPIO3 128151#define HI3670_PCLK_GPIO4 129152#define HI3670_PCLK_GPIO5 130153#define HI3670_PCLK_GPIO6 131154#define HI3670_PCLK_GPIO7 132155#define HI3670_PCLK_GPIO8 133156#define HI3670_PCLK_GPIO9 134157#define HI3670_PCLK_GPIO10 135158#define HI3670_PCLK_GPIO11 136159#define HI3670_PCLK_GPIO12 137160#define HI3670_PCLK_GPIO13 138161#define HI3670_PCLK_GPIO14 139162#define HI3670_PCLK_GPIO15 140163#define HI3670_PCLK_GPIO16 141164#define HI3670_PCLK_GPIO17 142165#define HI3670_PCLK_GPIO20 143166#define HI3670_PCLK_GPIO21 144167#define HI3670_PCLK_GATE_DSI0 145168#define HI3670_PCLK_GATE_DSI1 146169#define HI3670_HCLK_GATE_USB3OTG 147170#define HI3670_ACLK_GATE_USB3DVFS 148171#define HI3670_HCLK_GATE_SDIO 149172#define HI3670_PCLK_GATE_PCIE_SYS 150173#define HI3670_PCLK_GATE_PCIE_PHY 151174#define HI3670_PCLK_GATE_MMC1_PCIE 152175#define HI3670_PCLK_GATE_MMC0_IOC 153176#define HI3670_PCLK_GATE_MMC1_IOC 154177#define HI3670_CLK_GATE_DMAC 155178#define HI3670_CLK_GATE_VCODECBUS2DDR 156179#define HI3670_CLK_CCI400_BYPASS 157180#define HI3670_CLK_GATE_CCI400 158181#define HI3670_CLK_GATE_SD 159182#define HI3670_HCLK_GATE_SD 160183#define HI3670_CLK_GATE_SDIO 161184#define HI3670_CLK_GATE_A57HPM 162185#define HI3670_CLK_GATE_A53HPM 163186#define HI3670_CLK_GATE_PA_A53 164187#define HI3670_CLK_GATE_PA_A57 165188#define HI3670_CLK_GATE_PA_G3D 166189#define HI3670_CLK_GATE_GPUHPM 167190#define HI3670_CLK_GATE_PERIHPM 168191#define HI3670_CLK_GATE_AOHPM 169192#define HI3670_CLK_GATE_UART1 170193#define HI3670_CLK_GATE_UART4 171194#define HI3670_PCLK_GATE_UART1 172195#define HI3670_PCLK_GATE_UART4 173196#define HI3670_CLK_GATE_UART2 174197#define HI3670_CLK_GATE_UART5 175198#define HI3670_PCLK_GATE_UART2 176199#define HI3670_PCLK_GATE_UART5 177200#define HI3670_CLK_GATE_UART0 178201#define HI3670_CLK_GATE_I2C3 179202#define HI3670_CLK_GATE_I2C4 180203#define HI3670_CLK_GATE_I2C7 181204#define HI3670_PCLK_GATE_I2C3 182205#define HI3670_PCLK_GATE_I2C4 183206#define HI3670_PCLK_GATE_I2C7 184207#define HI3670_CLK_GATE_SPI1 185208#define HI3670_CLK_GATE_SPI4 186209#define HI3670_PCLK_GATE_SPI1 187210#define HI3670_PCLK_GATE_SPI4 188211#define HI3670_CLK_GATE_USB3OTG_REF 189212#define HI3670_CLK_GATE_USB2PHY_REF 190213#define HI3670_CLK_GATE_PCIEAUX 191214#define HI3670_ACLK_GATE_PCIE 192215#define HI3670_CLK_GATE_MMC1_PCIEAXI 193216#define HI3670_CLK_GATE_PCIEPHY_REF 194217#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195218#define HI3670_CLK_GATE_PCIEIO 196219#define HI3670_CLK_GATE_PCIE_HP 197220#define HI3670_CLK_GATE_AO_ASP 198221#define HI3670_PCLK_GATE_PCTRL 199222#define HI3670_CLK_CSI_TRANS_GT 200223#define HI3670_CLK_DSI_TRANS_GT 201224#define HI3670_CLK_GATE_PWM 202225#define HI3670_ABB_AUDIO_EN0 203226#define HI3670_ABB_AUDIO_EN1 204227#define HI3670_ABB_AUDIO_GT_EN0 205228#define HI3670_ABB_AUDIO_GT_EN1 206229#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207230#define HI3670_PERI_VOLT_HOLD 208231#define HI3670_PERI_VOLT_MIDDLE 209232#define HI3670_CLK_GATE_ISP_SNCLK0 210233#define HI3670_CLK_GATE_ISP_SNCLK1 211234#define HI3670_CLK_GATE_ISP_SNCLK2 212235#define HI3670_CLK_GATE_RXDPHY0_CFG 213236#define HI3670_CLK_GATE_RXDPHY1_CFG 214237#define HI3670_CLK_GATE_RXDPHY2_CFG 215238#define HI3670_CLK_GATE_TXDPHY0_CFG 216239#define HI3670_CLK_GATE_TXDPHY0_REF 217240#define HI3670_CLK_GATE_TXDPHY1_CFG 218241#define HI3670_CLK_GATE_TXDPHY1_REF 219242#define HI3670_CLK_GATE_MEDIA_TCXO 220243 244/* clk in sctrl */245#define HI3670_CLK_ANDGT_IOPERI 0246#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1247#define HI3670_CLK_ANGT_ASP_SUBSYS 2248#define HI3670_CLK_MUX_UFS_SUBSYS 3249#define HI3670_CLK_MUX_CLKOUT0 4250#define HI3670_CLK_MUX_CLKOUT1 5251#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6252#define HI3670_CLK_MUX_ASP_PLL 7253#define HI3670_CLK_DIV_AOBUS 8254#define HI3670_CLK_DIV_UFS_SUBSYS 9255#define HI3670_CLK_DIV_IOPERI 10256#define HI3670_CLK_DIV_CLKOUT0_TCXO 11257#define HI3670_CLK_DIV_CLKOUT1_TCXO 12258#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13259#define HI3670_CLK_DIV_ASP_SUBSYS 14260#define HI3670_PPLL0_EN_ACPU 15261#define HI3670_PPLL0_GT_CPU 16262#define HI3670_CLK_GATE_PPLL0_MEDIA 17263#define HI3670_PCLK_GPIO18 18264#define HI3670_PCLK_GPIO19 19265#define HI3670_CLK_GATE_SPI 20266#define HI3670_PCLK_GATE_SPI 21267#define HI3670_CLK_GATE_UFS_SUBSYS 22268#define HI3670_CLK_GATE_UFSIO_REF 23269#define HI3670_PCLK_AO_GPIO0 24270#define HI3670_PCLK_AO_GPIO1 25271#define HI3670_PCLK_AO_GPIO2 26272#define HI3670_PCLK_AO_GPIO3 27273#define HI3670_PCLK_AO_GPIO4 28274#define HI3670_PCLK_AO_GPIO5 29275#define HI3670_PCLK_AO_GPIO6 30276#define HI3670_CLK_GATE_OUT0 31277#define HI3670_CLK_GATE_OUT1 32278#define HI3670_PCLK_GATE_SYSCNT 33279#define HI3670_CLK_GATE_SYSCNT 34280#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35281#define HI3670_CLK_GATE_ASP_SUBSYS 36282#define HI3670_CLK_GATE_ASP_TCXO 37283#define HI3670_CLK_GATE_DP_AUDIO_PLL 38284 285/* clk in pmuctrl */286#define HI3670_GATE_ABB_192 0287 288/* clk in pctrl */289#define HI3670_GATE_UFS_TCXO_EN 0290#define HI3670_GATE_USB_TCXO_EN 1291 292/* clk in iomcu */293#define HI3670_CLK_GATE_I2C0 0294#define HI3670_CLK_GATE_I2C1 1295#define HI3670_CLK_GATE_I2C2 2296#define HI3670_CLK_GATE_SPI0 3297#define HI3670_CLK_GATE_SPI2 4298#define HI3670_CLK_GATE_UART3 5299#define HI3670_CLK_I2C0_GATE_IOMCU 6300#define HI3670_CLK_I2C1_GATE_IOMCU 7301#define HI3670_CLK_I2C2_GATE_IOMCU 8302#define HI3670_CLK_SPI0_GATE_IOMCU 9303#define HI3670_CLK_SPI2_GATE_IOMCU 10304#define HI3670_CLK_UART3_GATE_IOMCU 11305#define HI3670_CLK_GATE_PERI0_IOMCU 12306 307/* clk in media1 */308#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0309#define HI3670_CLK_ANDGT_EDC0 1310#define HI3670_CLK_ANDGT_LDI0 2311#define HI3670_CLK_ANDGT_LDI1 3312#define HI3670_CLK_MMBUF_PLL_ANDGT 4313#define HI3670_PCLK_MMBUF_ANDGT 5314#define HI3670_CLK_MUX_VIVOBUS 6315#define HI3670_CLK_MUX_EDC0 7316#define HI3670_CLK_MUX_LDI0 8317#define HI3670_CLK_MUX_LDI1 9318#define HI3670_CLK_SW_MMBUF 10319#define HI3670_CLK_DIV_VIVOBUS 11320#define HI3670_CLK_DIV_EDC0 12321#define HI3670_CLK_DIV_LDI0 13322#define HI3670_CLK_DIV_LDI1 14323#define HI3670_ACLK_DIV_MMBUF 15324#define HI3670_PCLK_DIV_MMBUF 16325#define HI3670_ACLK_GATE_NOC_DSS 17326#define HI3670_PCLK_GATE_NOC_DSS_CFG 18327#define HI3670_PCLK_GATE_MMBUF_CFG 19328#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20329#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21330#define HI3670_PCLK_GATE_DSS 22331#define HI3670_ACLK_GATE_DSS 23332#define HI3670_CLK_GATE_VIVOBUSFREQ 24333#define HI3670_CLK_GATE_EDC0 25334#define HI3670_CLK_GATE_LDI0 26335#define HI3670_CLK_GATE_LDI1FREQ 27336#define HI3670_CLK_GATE_BRG 28337#define HI3670_ACLK_GATE_ASC 29338#define HI3670_CLK_GATE_DSS_AXI_MM 30339#define HI3670_CLK_GATE_MMBUF 31340#define HI3670_PCLK_GATE_MMBUF 32341#define HI3670_CLK_GATE_ATDIV_VIVO 33342 343/* clk in media2 */344#define HI3670_CLK_GATE_VDECFREQ 0345#define HI3670_CLK_GATE_VENCFREQ 1346#define HI3670_CLK_GATE_ICSFREQ 2347 348#endif /* __DT_BINDINGS_CLOCK_HI3670_H */349