179 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2015 Hisilicon Limited.4 *5 * Author: Bintian Wang <bintian.wang@huawei.com>6 */7 8#ifndef __DT_BINDINGS_CLOCK_HI6220_H9#define __DT_BINDINGS_CLOCK_HI6220_H10 11/* clk in Hi6220 AO (always on) controller */12#define HI6220_NONE_CLOCK 013 14/* fixed rate clocks */15#define HI6220_REF32K 116#define HI6220_CLK_TCXO 217#define HI6220_MMC1_PAD 318#define HI6220_MMC2_PAD 419#define HI6220_MMC0_PAD 520#define HI6220_PLL_BBP 621#define HI6220_PLL_GPU 722#define HI6220_PLL1_DDR 823#define HI6220_PLL_SYS 924#define HI6220_PLL_SYS_MEDIA 1025#define HI6220_DDR_SRC 1126#define HI6220_PLL_MEDIA 1227#define HI6220_PLL_DDR 1328 29/* fixed factor clocks */30#define HI6220_300M 1431#define HI6220_150M 1532#define HI6220_PICOPHY_SRC 1633#define HI6220_MMC0_SRC_SEL 1734#define HI6220_MMC1_SRC_SEL 1835#define HI6220_MMC2_SRC_SEL 1936#define HI6220_VPU_CODEC 2037#define HI6220_MMC0_SMP 2138#define HI6220_MMC1_SMP 2239#define HI6220_MMC2_SMP 2340 41/* gate clocks */42#define HI6220_WDT0_PCLK 2443#define HI6220_WDT1_PCLK 2544#define HI6220_WDT2_PCLK 2645#define HI6220_TIMER0_PCLK 2746#define HI6220_TIMER1_PCLK 2847#define HI6220_TIMER2_PCLK 2948#define HI6220_TIMER3_PCLK 3049#define HI6220_TIMER4_PCLK 3150#define HI6220_TIMER5_PCLK 3251#define HI6220_TIMER6_PCLK 3352#define HI6220_TIMER7_PCLK 3453#define HI6220_TIMER8_PCLK 3554#define HI6220_UART0_PCLK 3655#define HI6220_RTC0_PCLK 3756#define HI6220_RTC1_PCLK 3857#define HI6220_AO_NR_CLKS 3958 59/* clk in Hi6220 systrl */60/* gate clock */61#define HI6220_MMC0_CLK 162#define HI6220_MMC0_CIUCLK 263#define HI6220_MMC1_CLK 364#define HI6220_MMC1_CIUCLK 465#define HI6220_MMC2_CLK 566#define HI6220_MMC2_CIUCLK 667#define HI6220_USBOTG_HCLK 768#define HI6220_CLK_PICOPHY 869#define HI6220_HIFI 970#define HI6220_DACODEC_PCLK 1071#define HI6220_EDMAC_ACLK 1172#define HI6220_CS_ATB 1273#define HI6220_I2C0_CLK 1374#define HI6220_I2C1_CLK 1475#define HI6220_I2C2_CLK 1576#define HI6220_I2C3_CLK 1677#define HI6220_UART1_PCLK 1778#define HI6220_UART2_PCLK 1879#define HI6220_UART3_PCLK 1980#define HI6220_UART4_PCLK 2081#define HI6220_SPI_CLK 2182#define HI6220_TSENSOR_CLK 2283#define HI6220_MMU_CLK 2384#define HI6220_HIFI_SEL 2485#define HI6220_MMC0_SYSPLL 2586#define HI6220_MMC1_SYSPLL 2687#define HI6220_MMC2_SYSPLL 2788#define HI6220_MMC0_SEL 2889#define HI6220_MMC1_SEL 2990#define HI6220_BBPPLL_SEL 3091#define HI6220_MEDIA_PLL_SRC 3192#define HI6220_MMC2_SEL 3293#define HI6220_CS_ATB_SYSPLL 3394 95/* mux clocks */96#define HI6220_MMC0_SRC 3497#define HI6220_MMC0_SMP_IN 3598#define HI6220_MMC1_SRC 3699#define HI6220_MMC1_SMP_IN 37100#define HI6220_MMC2_SRC 38101#define HI6220_MMC2_SMP_IN 39102#define HI6220_HIFI_SRC 40103#define HI6220_UART1_SRC 41104#define HI6220_UART2_SRC 42105#define HI6220_UART3_SRC 43106#define HI6220_UART4_SRC 44107#define HI6220_MMC0_MUX0 45108#define HI6220_MMC1_MUX0 46109#define HI6220_MMC2_MUX0 47110#define HI6220_MMC0_MUX1 48111#define HI6220_MMC1_MUX1 49112#define HI6220_MMC2_MUX1 50113 114/* divider clocks */115#define HI6220_CLK_BUS 51116#define HI6220_MMC0_DIV 52117#define HI6220_MMC1_DIV 53118#define HI6220_MMC2_DIV 54119#define HI6220_HIFI_DIV 55120#define HI6220_BBPPLL0_DIV 56121#define HI6220_CS_DAPB 57122#define HI6220_CS_ATB_DIV 58123 124/* gate clock */125#define HI6220_DAPB_CLK 59126 127#define HI6220_SYS_NR_CLKS 60128 129/* clk in Hi6220 media controller */130/* gate clocks */131#define HI6220_DSI_PCLK 1132#define HI6220_G3D_PCLK 2133#define HI6220_ACLK_CODEC_VPU 3134#define HI6220_ISP_SCLK 4135#define HI6220_ADE_CORE 5136#define HI6220_MED_MMU 6137#define HI6220_CFG_CSI4PHY 7138#define HI6220_CFG_CSI2PHY 8139#define HI6220_ISP_SCLK_GATE 9140#define HI6220_ISP_SCLK_GATE1 10141#define HI6220_ADE_CORE_GATE 11142#define HI6220_CODEC_VPU_GATE 12143#define HI6220_MED_SYSPLL 13144 145/* mux clocks */146#define HI6220_1440_1200 14147#define HI6220_1000_1200 15148#define HI6220_1000_1440 16149 150/* divider clocks */151#define HI6220_CODEC_JPEG 17152#define HI6220_ISP_SCLK_SRC 18153#define HI6220_ISP_SCLK1 19154#define HI6220_ADE_CORE_SRC 20155#define HI6220_ADE_PIX_SRC 21156#define HI6220_G3D_CLK 22157#define HI6220_CODEC_VPU_SRC 23158 159#define HI6220_MEDIA_NR_CLKS 24160 161/* clk in Hi6220 power controller */162/* gate clocks */163#define HI6220_PLL_GPU_GATE 1164#define HI6220_PLL1_DDR_GATE 2165#define HI6220_PLL_DDR_GATE 3166#define HI6220_PLL_MEDIA_GATE 4167#define HI6220_PLL0_BBP_GATE 5168 169/* divider clocks */170#define HI6220_DDRC_SRC 6171#define HI6220_DDRC_AXI1 7172 173#define HI6220_POWER_NR_CLKS 8174 175/* clk in Hi6220 acpu sctrl */176#define HI6220_ACPU_SFT_AT_S 0177 178#endif179