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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.4 */5 6#ifndef __DTS_HISTB_CLOCK_H7#define __DTS_HISTB_CLOCK_H8 9/* clocks provided by core CRG */10#define HISTB_OSC_CLK 011#define HISTB_APB_CLK 112#define HISTB_AHB_CLK 213#define HISTB_UART1_CLK 314#define HISTB_UART2_CLK 415#define HISTB_UART3_CLK 516#define HISTB_I2C0_CLK 617#define HISTB_I2C1_CLK 718#define HISTB_I2C2_CLK 819#define HISTB_I2C3_CLK 920#define HISTB_I2C4_CLK 1021#define HISTB_I2C5_CLK 1122#define HISTB_SPI0_CLK 1223#define HISTB_SPI1_CLK 1324#define HISTB_SPI2_CLK 1425#define HISTB_SCI_CLK 1526#define HISTB_FMC_CLK 1627#define HISTB_MMC_BIU_CLK 1728#define HISTB_MMC_CIU_CLK 1829#define HISTB_MMC_DRV_CLK 1930#define HISTB_MMC_SAMPLE_CLK 2031#define HISTB_SDIO0_BIU_CLK 2132#define HISTB_SDIO0_CIU_CLK 2233#define HISTB_SDIO0_DRV_CLK 2334#define HISTB_SDIO0_SAMPLE_CLK 2435#define HISTB_PCIE_AUX_CLK 2536#define HISTB_PCIE_PIPE_CLK 2637#define HISTB_PCIE_SYS_CLK 2738#define HISTB_PCIE_BUS_CLK 2839#define HISTB_ETH0_MAC_CLK 2940#define HISTB_ETH0_MACIF_CLK 3041#define HISTB_ETH1_MAC_CLK 3142#define HISTB_ETH1_MACIF_CLK 3243#define HISTB_COMBPHY1_CLK 3344#define HISTB_USB2_BUS_CLK 3445#define HISTB_USB2_PHY_CLK 3546#define HISTB_USB2_UTMI_CLK 3647#define HISTB_USB2_12M_CLK 3748#define HISTB_USB2_48M_CLK 3849#define HISTB_USB2_OTG_UTMI_CLK 3950#define HISTB_USB2_PHY1_REF_CLK 4051#define HISTB_USB2_PHY2_REF_CLK 4152#define HISTB_COMBPHY0_CLK 4253#define HISTB_USB3_BUS_CLK 4354#define HISTB_USB3_UTMI_CLK 4455#define HISTB_USB3_PIPE_CLK 4556#define HISTB_USB3_SUSPEND_CLK 4657#define HISTB_USB3_BUS_CLK1 4758#define HISTB_USB3_UTMI_CLK1 4859#define HISTB_USB3_PIPE_CLK1 4960#define HISTB_USB3_SUSPEND_CLK1 5061 62/* clocks provided by mcu CRG */63#define HISTB_MCE_CLK 164#define HISTB_IR_CLK 265#define HISTB_TIMER01_CLK 366#define HISTB_LEDC_CLK 467#define HISTB_UART0_CLK 568#define HISTB_LSADC_CLK 669 70#endif /* __DTS_HISTB_CLOCK_H */71