105 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>4 */5 6#ifndef __DT_BINDINGS_CLOCK_IMX27_H7#define __DT_BINDINGS_CLOCK_IMX27_H8 9#define IMX27_CLK_DUMMY 010#define IMX27_CLK_CKIH 111#define IMX27_CLK_CKIL 212#define IMX27_CLK_MPLL 313#define IMX27_CLK_SPLL 414#define IMX27_CLK_MPLL_MAIN2 515#define IMX27_CLK_AHB 616#define IMX27_CLK_IPG 717#define IMX27_CLK_NFC_DIV 818#define IMX27_CLK_PER1_DIV 919#define IMX27_CLK_PER2_DIV 1020#define IMX27_CLK_PER3_DIV 1121#define IMX27_CLK_PER4_DIV 1222#define IMX27_CLK_VPU_SEL 1323#define IMX27_CLK_VPU_DIV 1424#define IMX27_CLK_USB_DIV 1525#define IMX27_CLK_CPU_SEL 1626#define IMX27_CLK_CLKO_SEL 1727#define IMX27_CLK_CPU_DIV 1828#define IMX27_CLK_CLKO_DIV 1929#define IMX27_CLK_SSI1_SEL 2030#define IMX27_CLK_SSI2_SEL 2131#define IMX27_CLK_SSI1_DIV 2232#define IMX27_CLK_SSI2_DIV 2333#define IMX27_CLK_CLKO_EN 2434#define IMX27_CLK_SSI2_IPG_GATE 2535#define IMX27_CLK_SSI1_IPG_GATE 2636#define IMX27_CLK_SLCDC_IPG_GATE 2737#define IMX27_CLK_SDHC3_IPG_GATE 2838#define IMX27_CLK_SDHC2_IPG_GATE 2939#define IMX27_CLK_SDHC1_IPG_GATE 3040#define IMX27_CLK_SCC_IPG_GATE 3141#define IMX27_CLK_SAHARA_IPG_GATE 3242#define IMX27_CLK_RTC_IPG_GATE 3343#define IMX27_CLK_PWM_IPG_GATE 3444#define IMX27_CLK_OWIRE_IPG_GATE 3545#define IMX27_CLK_LCDC_IPG_GATE 3646#define IMX27_CLK_KPP_IPG_GATE 3747#define IMX27_CLK_IIM_IPG_GATE 3848#define IMX27_CLK_I2C2_IPG_GATE 3949#define IMX27_CLK_I2C1_IPG_GATE 4050#define IMX27_CLK_GPT6_IPG_GATE 4151#define IMX27_CLK_GPT5_IPG_GATE 4252#define IMX27_CLK_GPT4_IPG_GATE 4353#define IMX27_CLK_GPT3_IPG_GATE 4454#define IMX27_CLK_GPT2_IPG_GATE 4555#define IMX27_CLK_GPT1_IPG_GATE 4656#define IMX27_CLK_GPIO_IPG_GATE 4757#define IMX27_CLK_FEC_IPG_GATE 4858#define IMX27_CLK_EMMA_IPG_GATE 4959#define IMX27_CLK_DMA_IPG_GATE 5060#define IMX27_CLK_CSPI3_IPG_GATE 5161#define IMX27_CLK_CSPI2_IPG_GATE 5262#define IMX27_CLK_CSPI1_IPG_GATE 5363#define IMX27_CLK_NFC_BAUD_GATE 5464#define IMX27_CLK_SSI2_BAUD_GATE 5565#define IMX27_CLK_SSI1_BAUD_GATE 5666#define IMX27_CLK_VPU_BAUD_GATE 5767#define IMX27_CLK_PER4_GATE 5868#define IMX27_CLK_PER3_GATE 5969#define IMX27_CLK_PER2_GATE 6070#define IMX27_CLK_PER1_GATE 6171#define IMX27_CLK_USB_AHB_GATE 6272#define IMX27_CLK_SLCDC_AHB_GATE 6373#define IMX27_CLK_SAHARA_AHB_GATE 6474#define IMX27_CLK_LCDC_AHB_GATE 6575#define IMX27_CLK_VPU_AHB_GATE 6676#define IMX27_CLK_FEC_AHB_GATE 6777#define IMX27_CLK_EMMA_AHB_GATE 6878#define IMX27_CLK_EMI_AHB_GATE 6979#define IMX27_CLK_DMA_AHB_GATE 7080#define IMX27_CLK_CSI_AHB_GATE 7181#define IMX27_CLK_BROM_AHB_GATE 7282#define IMX27_CLK_ATA_AHB_GATE 7383#define IMX27_CLK_WDOG_IPG_GATE 7484#define IMX27_CLK_USB_IPG_GATE 7585#define IMX27_CLK_UART6_IPG_GATE 7686#define IMX27_CLK_UART5_IPG_GATE 7787#define IMX27_CLK_UART4_IPG_GATE 7888#define IMX27_CLK_UART3_IPG_GATE 7989#define IMX27_CLK_UART2_IPG_GATE 8090#define IMX27_CLK_UART1_IPG_GATE 8191#define IMX27_CLK_CKIH_DIV1P5 8292#define IMX27_CLK_FPM 8393#define IMX27_CLK_MPLL_OSC_SEL 8494#define IMX27_CLK_MPLL_SEL 8595#define IMX27_CLK_SPLL_GATE 8696#define IMX27_CLK_MSHC_DIV 8797#define IMX27_CLK_RTIC_IPG_GATE 8898#define IMX27_CLK_MSHC_IPG_GATE 8999#define IMX27_CLK_RTIC_AHB_GATE 90100#define IMX27_CLK_MSHC_BAUD_GATE 91101#define IMX27_CLK_CKIH_GATE 92102#define IMX27_CLK_MAX 93103 104#endif105