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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>4 */5 6#ifndef __DT_BINDINGS_CLOCK_IMX5_H7#define __DT_BINDINGS_CLOCK_IMX5_H8 9#define IMX5_CLK_DUMMY 010#define IMX5_CLK_CKIL 111#define IMX5_CLK_OSC 212#define IMX5_CLK_CKIH1 313#define IMX5_CLK_CKIH2 414#define IMX5_CLK_AHB 515#define IMX5_CLK_IPG 616#define IMX5_CLK_AXI_A 717#define IMX5_CLK_AXI_B 818#define IMX5_CLK_UART_PRED 919#define IMX5_CLK_UART_ROOT 1020#define IMX5_CLK_ESDHC_A_PRED 1121#define IMX5_CLK_ESDHC_B_PRED 1222#define IMX5_CLK_ESDHC_C_SEL 1323#define IMX5_CLK_ESDHC_D_SEL 1424#define IMX5_CLK_EMI_SEL 1525#define IMX5_CLK_EMI_SLOW_PODF 1626#define IMX5_CLK_NFC_PODF 1727#define IMX5_CLK_ECSPI_PRED 1828#define IMX5_CLK_ECSPI_PODF 1929#define IMX5_CLK_USBOH3_PRED 2030#define IMX5_CLK_USBOH3_PODF 2131#define IMX5_CLK_USB_PHY_PRED 2232#define IMX5_CLK_USB_PHY_PODF 2333#define IMX5_CLK_CPU_PODF 2434#define IMX5_CLK_DI_PRED 2535#define IMX5_CLK_TVE_SEL 2736#define IMX5_CLK_UART1_IPG_GATE 2837#define IMX5_CLK_UART1_PER_GATE 2938#define IMX5_CLK_UART2_IPG_GATE 3039#define IMX5_CLK_UART2_PER_GATE 3140#define IMX5_CLK_UART3_IPG_GATE 3241#define IMX5_CLK_UART3_PER_GATE 3342#define IMX5_CLK_I2C1_GATE 3443#define IMX5_CLK_I2C2_GATE 3544#define IMX5_CLK_GPT_IPG_GATE 3645#define IMX5_CLK_PWM1_IPG_GATE 3746#define IMX5_CLK_PWM1_HF_GATE 3847#define IMX5_CLK_PWM2_IPG_GATE 3948#define IMX5_CLK_PWM2_HF_GATE 4049#define IMX5_CLK_GPT_HF_GATE 4150#define IMX5_CLK_FEC_GATE 4251#define IMX5_CLK_USBOH3_PER_GATE 4352#define IMX5_CLK_ESDHC1_IPG_GATE 4453#define IMX5_CLK_ESDHC2_IPG_GATE 4554#define IMX5_CLK_ESDHC3_IPG_GATE 4655#define IMX5_CLK_ESDHC4_IPG_GATE 4756#define IMX5_CLK_SSI1_IPG_GATE 4857#define IMX5_CLK_SSI2_IPG_GATE 4958#define IMX5_CLK_SSI3_IPG_GATE 5059#define IMX5_CLK_ECSPI1_IPG_GATE 5160#define IMX5_CLK_ECSPI1_PER_GATE 5261#define IMX5_CLK_ECSPI2_IPG_GATE 5362#define IMX5_CLK_ECSPI2_PER_GATE 5463#define IMX5_CLK_CSPI_IPG_GATE 5564#define IMX5_CLK_SDMA_GATE 5665#define IMX5_CLK_EMI_SLOW_GATE 5766#define IMX5_CLK_IPU_SEL 5867#define IMX5_CLK_IPU_GATE 5968#define IMX5_CLK_NFC_GATE 6069#define IMX5_CLK_IPU_DI1_GATE 6170#define IMX5_CLK_VPU_SEL 6271#define IMX5_CLK_VPU_GATE 6372#define IMX5_CLK_VPU_REFERENCE_GATE 6473#define IMX5_CLK_UART4_IPG_GATE 6574#define IMX5_CLK_UART4_PER_GATE 6675#define IMX5_CLK_UART5_IPG_GATE 6776#define IMX5_CLK_UART5_PER_GATE 6877#define IMX5_CLK_TVE_GATE 6978#define IMX5_CLK_TVE_PRED 7079#define IMX5_CLK_ESDHC1_PER_GATE 7180#define IMX5_CLK_ESDHC2_PER_GATE 7281#define IMX5_CLK_ESDHC3_PER_GATE 7382#define IMX5_CLK_ESDHC4_PER_GATE 7483#define IMX5_CLK_USB_PHY_GATE 7584#define IMX5_CLK_HSI2C_GATE 7685#define IMX5_CLK_MIPI_HSC1_GATE 7786#define IMX5_CLK_MIPI_HSC2_GATE 7887#define IMX5_CLK_MIPI_ESC_GATE 7988#define IMX5_CLK_MIPI_HSP_GATE 8089#define IMX5_CLK_LDB_DI1_DIV_3_5 8190#define IMX5_CLK_LDB_DI1_DIV 8291#define IMX5_CLK_LDB_DI0_DIV_3_5 8392#define IMX5_CLK_LDB_DI0_DIV 8493#define IMX5_CLK_LDB_DI1_GATE 8594#define IMX5_CLK_CAN2_SERIAL_GATE 8695#define IMX5_CLK_CAN2_IPG_GATE 8796#define IMX5_CLK_I2C3_GATE 8897#define IMX5_CLK_LP_APM 8998#define IMX5_CLK_PERIPH_APM 9099#define IMX5_CLK_MAIN_BUS 91100#define IMX5_CLK_AHB_MAX 92101#define IMX5_CLK_AIPS_TZ1 93102#define IMX5_CLK_AIPS_TZ2 94103#define IMX5_CLK_TMAX1 95104#define IMX5_CLK_TMAX2 96105#define IMX5_CLK_TMAX3 97106#define IMX5_CLK_SPBA 98107#define IMX5_CLK_UART_SEL 99108#define IMX5_CLK_ESDHC_A_SEL 100109#define IMX5_CLK_ESDHC_B_SEL 101110#define IMX5_CLK_ESDHC_A_PODF 102111#define IMX5_CLK_ESDHC_B_PODF 103112#define IMX5_CLK_ECSPI_SEL 104113#define IMX5_CLK_USBOH3_SEL 105114#define IMX5_CLK_USB_PHY_SEL 106115#define IMX5_CLK_IIM_GATE 107116#define IMX5_CLK_USBOH3_GATE 108117#define IMX5_CLK_EMI_FAST_GATE 109118#define IMX5_CLK_IPU_DI0_GATE 110119#define IMX5_CLK_GPC_DVFS 111120#define IMX5_CLK_PLL1_SW 112121#define IMX5_CLK_PLL2_SW 113122#define IMX5_CLK_PLL3_SW 114123#define IMX5_CLK_IPU_DI0_SEL 115124#define IMX5_CLK_IPU_DI1_SEL 116125#define IMX5_CLK_TVE_EXT_SEL 117126#define IMX5_CLK_MX51_MIPI 118127#define IMX5_CLK_PLL4_SW 119128#define IMX5_CLK_LDB_DI1_SEL 120129#define IMX5_CLK_DI_PLL4_PODF 121130#define IMX5_CLK_LDB_DI0_SEL 122131#define IMX5_CLK_LDB_DI0_GATE 123132#define IMX5_CLK_USB_PHY1_GATE 124133#define IMX5_CLK_USB_PHY2_GATE 125134#define IMX5_CLK_PER_LP_APM 126135#define IMX5_CLK_PER_PRED1 127136#define IMX5_CLK_PER_PRED2 128137#define IMX5_CLK_PER_PODF 129138#define IMX5_CLK_PER_ROOT 130139#define IMX5_CLK_SSI_APM 131140#define IMX5_CLK_SSI1_ROOT_SEL 132141#define IMX5_CLK_SSI2_ROOT_SEL 133142#define IMX5_CLK_SSI3_ROOT_SEL 134143#define IMX5_CLK_SSI_EXT1_SEL 135144#define IMX5_CLK_SSI_EXT2_SEL 136145#define IMX5_CLK_SSI_EXT1_COM_SEL 137146#define IMX5_CLK_SSI_EXT2_COM_SEL 138147#define IMX5_CLK_SSI1_ROOT_PRED 139148#define IMX5_CLK_SSI1_ROOT_PODF 140149#define IMX5_CLK_SSI2_ROOT_PRED 141150#define IMX5_CLK_SSI2_ROOT_PODF 142151#define IMX5_CLK_SSI_EXT1_PRED 143152#define IMX5_CLK_SSI_EXT1_PODF 144153#define IMX5_CLK_SSI_EXT2_PRED 145154#define IMX5_CLK_SSI_EXT2_PODF 146155#define IMX5_CLK_SSI1_ROOT_GATE 147156#define IMX5_CLK_SSI2_ROOT_GATE 148157#define IMX5_CLK_SSI3_ROOT_GATE 149158#define IMX5_CLK_SSI_EXT1_GATE 150159#define IMX5_CLK_SSI_EXT2_GATE 151160#define IMX5_CLK_EPIT1_IPG_GATE 152161#define IMX5_CLK_EPIT1_HF_GATE 153162#define IMX5_CLK_EPIT2_IPG_GATE 154163#define IMX5_CLK_EPIT2_HF_GATE 155164#define IMX5_CLK_CAN_SEL 156165#define IMX5_CLK_CAN1_SERIAL_GATE 157166#define IMX5_CLK_CAN1_IPG_GATE 158167#define IMX5_CLK_OWIRE_GATE 159168#define IMX5_CLK_GPU3D_SEL 160169#define IMX5_CLK_GPU2D_SEL 161170#define IMX5_CLK_GPU3D_GATE 162171#define IMX5_CLK_GPU2D_GATE 163172#define IMX5_CLK_GARB_GATE 164173#define IMX5_CLK_CKO1_SEL 165174#define IMX5_CLK_CKO1_PODF 166175#define IMX5_CLK_CKO1 167176#define IMX5_CLK_CKO2_SEL 168177#define IMX5_CLK_CKO2_PODF 169178#define IMX5_CLK_CKO2 170179#define IMX5_CLK_SRTC_GATE 171180#define IMX5_CLK_PATA_GATE 172181#define IMX5_CLK_SATA_GATE 173182#define IMX5_CLK_SPDIF_XTAL_SEL 174183#define IMX5_CLK_SPDIF0_SEL 175184#define IMX5_CLK_SPDIF1_SEL 176185#define IMX5_CLK_SPDIF0_PRED 177186#define IMX5_CLK_SPDIF0_PODF 178187#define IMX5_CLK_SPDIF1_PRED 179188#define IMX5_CLK_SPDIF1_PODF 180189#define IMX5_CLK_SPDIF0_COM_SEL 181190#define IMX5_CLK_SPDIF1_COM_SEL 182191#define IMX5_CLK_SPDIF0_GATE 183192#define IMX5_CLK_SPDIF1_GATE 184193#define IMX5_CLK_SPDIF_IPG_GATE 185194#define IMX5_CLK_OCRAM 186195#define IMX5_CLK_SAHARA_IPG_GATE 187196#define IMX5_CLK_SATA_REF 188197#define IMX5_CLK_STEP_SEL 189198#define IMX5_CLK_CPU_PODF_SEL 190199#define IMX5_CLK_ARM 191200#define IMX5_CLK_FIRI_PRED 192201#define IMX5_CLK_FIRI_SEL 193202#define IMX5_CLK_FIRI_PODF 194203#define IMX5_CLK_FIRI_SERIAL_GATE 195204#define IMX5_CLK_FIRI_IPG_GATE 196205#define IMX5_CLK_CSI0_MCLK1_PRED 197206#define IMX5_CLK_CSI0_MCLK1_SEL 198207#define IMX5_CLK_CSI0_MCLK1_PODF 199208#define IMX5_CLK_CSI0_MCLK1_GATE 200209#define IMX5_CLK_IEEE1588_PRED 201210#define IMX5_CLK_IEEE1588_SEL 202211#define IMX5_CLK_IEEE1588_PODF 203212#define IMX5_CLK_IEEE1588_GATE 204213#define IMX5_CLK_SCC2_IPG_GATE 205214#define IMX5_CLK_END 206215 216#endif /* __DT_BINDINGS_CLOCK_IMX5_H */217