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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Copyright (C) 2016 Freescale Semiconductor, Inc.4 * Copyright 2017~2018 NXP5 *6 */7 8#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H9#define __DT_BINDINGS_CLOCK_IMX7ULP_H10 11/* SCG1 */12 13#define IMX7ULP_CLK_DUMMY 014#define IMX7ULP_CLK_ROSC 115#define IMX7ULP_CLK_SOSC 216#define IMX7ULP_CLK_FIRC 317#define IMX7ULP_CLK_SPLL_PRE_SEL 418#define IMX7ULP_CLK_SPLL_PRE_DIV 519#define IMX7ULP_CLK_SPLL 620#define IMX7ULP_CLK_SPLL_POST_DIV1 721#define IMX7ULP_CLK_SPLL_POST_DIV2 822#define IMX7ULP_CLK_SPLL_PFD0 923#define IMX7ULP_CLK_SPLL_PFD1 1024#define IMX7ULP_CLK_SPLL_PFD2 1125#define IMX7ULP_CLK_SPLL_PFD3 1226#define IMX7ULP_CLK_SPLL_PFD_SEL 1327#define IMX7ULP_CLK_SPLL_SEL 1428#define IMX7ULP_CLK_APLL_PRE_SEL 1529#define IMX7ULP_CLK_APLL_PRE_DIV 1630#define IMX7ULP_CLK_APLL 1731#define IMX7ULP_CLK_APLL_POST_DIV1 1832#define IMX7ULP_CLK_APLL_POST_DIV2 1933#define IMX7ULP_CLK_APLL_PFD0 2034#define IMX7ULP_CLK_APLL_PFD1 2135#define IMX7ULP_CLK_APLL_PFD2 2236#define IMX7ULP_CLK_APLL_PFD3 2337#define IMX7ULP_CLK_APLL_PFD_SEL 2438#define IMX7ULP_CLK_APLL_SEL 2539#define IMX7ULP_CLK_UPLL 2640#define IMX7ULP_CLK_SYS_SEL 2741#define IMX7ULP_CLK_CORE_DIV 2842#define IMX7ULP_CLK_BUS_DIV 2943#define IMX7ULP_CLK_PLAT_DIV 3044#define IMX7ULP_CLK_DDR_SEL 3145#define IMX7ULP_CLK_DDR_DIV 3246#define IMX7ULP_CLK_NIC_SEL 3347#define IMX7ULP_CLK_NIC0_DIV 3448#define IMX7ULP_CLK_GPU_DIV 3549#define IMX7ULP_CLK_NIC1_DIV 3650#define IMX7ULP_CLK_NIC1_BUS_DIV 3751#define IMX7ULP_CLK_NIC1_EXT_DIV 3852/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */53#define IMX7ULP_CLK_MIPI_PLL 3954#define IMX7ULP_CLK_SIRC 4055#define IMX7ULP_CLK_SOSC_BUS_CLK 4156#define IMX7ULP_CLK_FIRC_BUS_CLK 4257#define IMX7ULP_CLK_SPLL_BUS_CLK 4358#define IMX7ULP_CLK_HSRUN_SYS_SEL 4459#define IMX7ULP_CLK_HSRUN_CORE_DIV 4560 61#define IMX7ULP_CLK_CORE 4662#define IMX7ULP_CLK_HSRUN_CORE 4763 64#define IMX7ULP_CLK_SCG1_END 4865 66/* PCC2 */67#define IMX7ULP_CLK_DMA1 068#define IMX7ULP_CLK_RGPIO2P1 169#define IMX7ULP_CLK_FLEXBUS 270#define IMX7ULP_CLK_SEMA42_1 371#define IMX7ULP_CLK_DMA_MUX1 472#define IMX7ULP_CLK_CAAM 673#define IMX7ULP_CLK_LPTPM4 774#define IMX7ULP_CLK_LPTPM5 875#define IMX7ULP_CLK_LPIT1 976#define IMX7ULP_CLK_LPSPI2 1077#define IMX7ULP_CLK_LPSPI3 1178#define IMX7ULP_CLK_LPI2C4 1279#define IMX7ULP_CLK_LPI2C5 1380#define IMX7ULP_CLK_LPUART4 1481#define IMX7ULP_CLK_LPUART5 1582#define IMX7ULP_CLK_FLEXIO1 1683#define IMX7ULP_CLK_USB0 1784#define IMX7ULP_CLK_USB1 1885#define IMX7ULP_CLK_USB_PHY 1986#define IMX7ULP_CLK_USB_PL301 2087#define IMX7ULP_CLK_USDHC0 2188#define IMX7ULP_CLK_USDHC1 2289#define IMX7ULP_CLK_WDG1 2390#define IMX7ULP_CLK_WDG2 2491 92#define IMX7ULP_CLK_PCC2_END 2593 94/* PCC3 */95#define IMX7ULP_CLK_LPTPM6 096#define IMX7ULP_CLK_LPTPM7 197#define IMX7ULP_CLK_LPI2C6 298#define IMX7ULP_CLK_LPI2C7 399#define IMX7ULP_CLK_LPUART6 4100#define IMX7ULP_CLK_LPUART7 5101#define IMX7ULP_CLK_VIU 6102#define IMX7ULP_CLK_DSI 7103#define IMX7ULP_CLK_LCDIF 8104#define IMX7ULP_CLK_MMDC 9105#define IMX7ULP_CLK_PCTLC 10106#define IMX7ULP_CLK_PCTLD 11107#define IMX7ULP_CLK_PCTLE 12108#define IMX7ULP_CLK_PCTLF 13109#define IMX7ULP_CLK_GPU3D 14110#define IMX7ULP_CLK_GPU2D 15111 112#define IMX7ULP_CLK_PCC3_END 16113 114/* SMC1 */115#define IMX7ULP_CLK_ARM 0116 117#define IMX7ULP_CLK_SMC1_END 1118 119#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */120