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1/* SPDX-License-Identifier: GPL-2.0+ OR MIT */2/*3 * Copyright 2021 NXP4 */5 6#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H7#define __DT_BINDINGS_CLOCK_IMX8ULP_H8 9#define IMX8ULP_CLK_DUMMY 010 11/* CGC1 */12#define IMX8ULP_CLK_SPLL2 513#define IMX8ULP_CLK_SPLL3 614#define IMX8ULP_CLK_A35_SEL 715#define IMX8ULP_CLK_A35_DIV 816#define IMX8ULP_CLK_SPLL2_PRE_SEL 917#define IMX8ULP_CLK_SPLL3_PRE_SEL 1018#define IMX8ULP_CLK_SPLL3_PFD0 1119#define IMX8ULP_CLK_SPLL3_PFD1 1220#define IMX8ULP_CLK_SPLL3_PFD2 1321#define IMX8ULP_CLK_SPLL3_PFD3 1422#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 1523#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 1624#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 1725#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 1826#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 1927#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 2028#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 2129#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 2230#define IMX8ULP_CLK_NIC_SEL 2331#define IMX8ULP_CLK_NIC_AD_DIVPLAT 2432#define IMX8ULP_CLK_NIC_PER_DIVPLAT 2533#define IMX8ULP_CLK_XBAR_SEL 2634#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 2735#define IMX8ULP_CLK_XBAR_DIVBUS 2836#define IMX8ULP_CLK_XBAR_AD_SLOW 2937#define IMX8ULP_CLK_SOSC_DIV1 3038#define IMX8ULP_CLK_SOSC_DIV2 3139#define IMX8ULP_CLK_SOSC_DIV3 3240#define IMX8ULP_CLK_FROSC_DIV1 3341#define IMX8ULP_CLK_FROSC_DIV2 3442#define IMX8ULP_CLK_FROSC_DIV3 3543#define IMX8ULP_CLK_SPLL3_VCODIV 3644#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 3745#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 3846#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 3947#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 4048#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 4149#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 4250#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 4351#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 4452#define IMX8ULP_CLK_SOSC_DIV1_GATE 4553#define IMX8ULP_CLK_SOSC_DIV2_GATE 4654#define IMX8ULP_CLK_SOSC_DIV3_GATE 4755#define IMX8ULP_CLK_FROSC_DIV1_GATE 4856#define IMX8ULP_CLK_FROSC_DIV2_GATE 4957#define IMX8ULP_CLK_FROSC_DIV3_GATE 5058#define IMX8ULP_CLK_SAI4_SEL 5159#define IMX8ULP_CLK_SAI5_SEL 5260#define IMX8ULP_CLK_AUD_CLK1 5361#define IMX8ULP_CLK_ARM 5462#define IMX8ULP_CLK_ENET_TS_SEL 5563 64#define IMX8ULP_CLK_CGC1_END 5665 66/* CGC2 */67#define IMX8ULP_CLK_PLL4_PRE_SEL 068#define IMX8ULP_CLK_PLL4 169#define IMX8ULP_CLK_PLL4_VCODIV 270#define IMX8ULP_CLK_DDR_SEL 371#define IMX8ULP_CLK_DDR_DIV 472#define IMX8ULP_CLK_LPAV_AXI_SEL 573#define IMX8ULP_CLK_LPAV_AXI_DIV 674#define IMX8ULP_CLK_LPAV_AHB_DIV 775#define IMX8ULP_CLK_LPAV_BUS_DIV 876#define IMX8ULP_CLK_PLL4_PFD0 977#define IMX8ULP_CLK_PLL4_PFD1 1078#define IMX8ULP_CLK_PLL4_PFD2 1179#define IMX8ULP_CLK_PLL4_PFD3 1280#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 1381#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 1482#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 1583#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 1684#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 1785#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 1886#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 1987#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 2088#define IMX8ULP_CLK_PLL4_PFD0_DIV1 2189#define IMX8ULP_CLK_PLL4_PFD0_DIV2 2290#define IMX8ULP_CLK_PLL4_PFD1_DIV1 2391#define IMX8ULP_CLK_PLL4_PFD1_DIV2 2492#define IMX8ULP_CLK_PLL4_PFD2_DIV1 2593#define IMX8ULP_CLK_PLL4_PFD2_DIV2 2694#define IMX8ULP_CLK_PLL4_PFD3_DIV1 2795#define IMX8ULP_CLK_PLL4_PFD3_DIV2 2896#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 2997#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 3098#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 3199#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32100#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33101#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34102#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35103#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36104#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37105#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38106#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39107#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40108#define IMX8ULP_CLK_AUD_CLK2 41109#define IMX8ULP_CLK_SAI6_SEL 42110#define IMX8ULP_CLK_SAI7_SEL 43111#define IMX8ULP_CLK_SPDIF_SEL 44112#define IMX8ULP_CLK_HIFI_SEL 45113#define IMX8ULP_CLK_HIFI_DIVCORE 46114#define IMX8ULP_CLK_HIFI_DIVPLAT 47115#define IMX8ULP_CLK_DSI_PHY_REF 48116 117#define IMX8ULP_CLK_CGC2_END 49118 119/* PCC3 */120#define IMX8ULP_CLK_WDOG3 0121#define IMX8ULP_CLK_WDOG4 1122#define IMX8ULP_CLK_LPIT1 2123#define IMX8ULP_CLK_TPM4 3124#define IMX8ULP_CLK_TPM5 4125#define IMX8ULP_CLK_FLEXIO1 5126#define IMX8ULP_CLK_I3C2 6127#define IMX8ULP_CLK_LPI2C4 7128#define IMX8ULP_CLK_LPI2C5 8129#define IMX8ULP_CLK_LPUART4 9130#define IMX8ULP_CLK_LPUART5 10131#define IMX8ULP_CLK_LPSPI4 11132#define IMX8ULP_CLK_LPSPI5 12133#define IMX8ULP_CLK_DMA1_MP 13134#define IMX8ULP_CLK_DMA1_CH0 14135#define IMX8ULP_CLK_DMA1_CH1 15136#define IMX8ULP_CLK_DMA1_CH2 16137#define IMX8ULP_CLK_DMA1_CH3 17138#define IMX8ULP_CLK_DMA1_CH4 18139#define IMX8ULP_CLK_DMA1_CH5 19140#define IMX8ULP_CLK_DMA1_CH6 20141#define IMX8ULP_CLK_DMA1_CH7 21142#define IMX8ULP_CLK_DMA1_CH8 22143#define IMX8ULP_CLK_DMA1_CH9 23144#define IMX8ULP_CLK_DMA1_CH10 24145#define IMX8ULP_CLK_DMA1_CH11 25146#define IMX8ULP_CLK_DMA1_CH12 26147#define IMX8ULP_CLK_DMA1_CH13 27148#define IMX8ULP_CLK_DMA1_CH14 28149#define IMX8ULP_CLK_DMA1_CH15 29150#define IMX8ULP_CLK_DMA1_CH16 30151#define IMX8ULP_CLK_DMA1_CH17 31152#define IMX8ULP_CLK_DMA1_CH18 32153#define IMX8ULP_CLK_DMA1_CH19 33154#define IMX8ULP_CLK_DMA1_CH20 34155#define IMX8ULP_CLK_DMA1_CH21 35156#define IMX8ULP_CLK_DMA1_CH22 36157#define IMX8ULP_CLK_DMA1_CH23 37158#define IMX8ULP_CLK_DMA1_CH24 38159#define IMX8ULP_CLK_DMA1_CH25 39160#define IMX8ULP_CLK_DMA1_CH26 40161#define IMX8ULP_CLK_DMA1_CH27 41162#define IMX8ULP_CLK_DMA1_CH28 42163#define IMX8ULP_CLK_DMA1_CH29 43164#define IMX8ULP_CLK_DMA1_CH30 44165#define IMX8ULP_CLK_DMA1_CH31 45166#define IMX8ULP_CLK_MU3_A 46167#define IMX8ULP_CLK_MU0_B 47168 169#define IMX8ULP_CLK_PCC3_END 48170 171/* PCC4 */172#define IMX8ULP_CLK_FLEXSPI2 0173#define IMX8ULP_CLK_TPM6 1174#define IMX8ULP_CLK_TPM7 2175#define IMX8ULP_CLK_LPI2C6 3176#define IMX8ULP_CLK_LPI2C7 4177#define IMX8ULP_CLK_LPUART6 5178#define IMX8ULP_CLK_LPUART7 6179#define IMX8ULP_CLK_SAI4 7180#define IMX8ULP_CLK_SAI5 8181#define IMX8ULP_CLK_PCTLE 9182#define IMX8ULP_CLK_PCTLF 10183#define IMX8ULP_CLK_USDHC0 11184#define IMX8ULP_CLK_USDHC1 12185#define IMX8ULP_CLK_USDHC2 13186#define IMX8ULP_CLK_USB0 14187#define IMX8ULP_CLK_USB0_PHY 15188#define IMX8ULP_CLK_USB1 16189#define IMX8ULP_CLK_USB1_PHY 17190#define IMX8ULP_CLK_USB_XBAR 18191#define IMX8ULP_CLK_ENET 19192#define IMX8ULP_CLK_SFA1 20193#define IMX8ULP_CLK_RGPIOE 21194#define IMX8ULP_CLK_RGPIOF 22195 196#define IMX8ULP_CLK_PCC4_END 23197 198/* PCC5 */199#define IMX8ULP_CLK_TPM8 0200#define IMX8ULP_CLK_SAI6 1201#define IMX8ULP_CLK_SAI7 2202#define IMX8ULP_CLK_SPDIF 3203#define IMX8ULP_CLK_ISI 4204#define IMX8ULP_CLK_CSI_REGS 5205#define IMX8ULP_CLK_PCTLD 6206#define IMX8ULP_CLK_CSI 7207#define IMX8ULP_CLK_DSI 8208#define IMX8ULP_CLK_WDOG5 9209#define IMX8ULP_CLK_EPDC 10210#define IMX8ULP_CLK_PXP 11211#define IMX8ULP_CLK_SFA2 12212#define IMX8ULP_CLK_GPU2D 13213#define IMX8ULP_CLK_GPU3D 14214#define IMX8ULP_CLK_DC_NANO 15215#define IMX8ULP_CLK_CSI_CLK_UI 16216#define IMX8ULP_CLK_CSI_CLK_ESC 17217#define IMX8ULP_CLK_RGPIOD 18218#define IMX8ULP_CLK_DMA2_MP 19219#define IMX8ULP_CLK_DMA2_CH0 20220#define IMX8ULP_CLK_DMA2_CH1 21221#define IMX8ULP_CLK_DMA2_CH2 22222#define IMX8ULP_CLK_DMA2_CH3 23223#define IMX8ULP_CLK_DMA2_CH4 24224#define IMX8ULP_CLK_DMA2_CH5 25225#define IMX8ULP_CLK_DMA2_CH6 26226#define IMX8ULP_CLK_DMA2_CH7 27227#define IMX8ULP_CLK_DMA2_CH8 28228#define IMX8ULP_CLK_DMA2_CH9 29229#define IMX8ULP_CLK_DMA2_CH10 30230#define IMX8ULP_CLK_DMA2_CH11 31231#define IMX8ULP_CLK_DMA2_CH12 32232#define IMX8ULP_CLK_DMA2_CH13 33233#define IMX8ULP_CLK_DMA2_CH14 34234#define IMX8ULP_CLK_DMA2_CH15 35235#define IMX8ULP_CLK_DMA2_CH16 36236#define IMX8ULP_CLK_DMA2_CH17 37237#define IMX8ULP_CLK_DMA2_CH18 38238#define IMX8ULP_CLK_DMA2_CH19 39239#define IMX8ULP_CLK_DMA2_CH20 40240#define IMX8ULP_CLK_DMA2_CH21 41241#define IMX8ULP_CLK_DMA2_CH22 42242#define IMX8ULP_CLK_DMA2_CH23 43243#define IMX8ULP_CLK_DMA2_CH24 44244#define IMX8ULP_CLK_DMA2_CH25 45245#define IMX8ULP_CLK_DMA2_CH26 46246#define IMX8ULP_CLK_DMA2_CH27 47247#define IMX8ULP_CLK_DMA2_CH28 48248#define IMX8ULP_CLK_DMA2_CH29 49249#define IMX8ULP_CLK_DMA2_CH30 50250#define IMX8ULP_CLK_DMA2_CH31 51251#define IMX8ULP_CLK_MU2_B 52252#define IMX8ULP_CLK_MU3_B 53253#define IMX8ULP_CLK_AVD_SIM 54254#define IMX8ULP_CLK_DSI_TX_ESC 55255 256#define IMX8ULP_CLK_PCC5_END 56257 258#endif259