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1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */2/*3 * Copyright(C) 20194 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>5 */6 7#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H8#define __DT_BINDINGS_CLOCK_IMXRT1050_H9 10#define IMXRT1050_CLK_DUMMY 011#define IMXRT1050_CLK_CKIL 112#define IMXRT1050_CLK_CKIH 213#define IMXRT1050_CLK_OSC 314#define IMXRT1050_CLK_PLL2_PFD0_352M 415#define IMXRT1050_CLK_PLL2_PFD1_594M 516#define IMXRT1050_CLK_PLL2_PFD2_396M 617#define IMXRT1050_CLK_PLL3_PFD0_720M 718#define IMXRT1050_CLK_PLL3_PFD1_664_62M 819#define IMXRT1050_CLK_PLL3_PFD2_508_24M 920#define IMXRT1050_CLK_PLL3_PFD3_454_74M 1021#define IMXRT1050_CLK_PLL2_198M 1122#define IMXRT1050_CLK_PLL3_120M 1223#define IMXRT1050_CLK_PLL3_80M 1324#define IMXRT1050_CLK_PLL3_60M 1425#define IMXRT1050_CLK_PLL1_BYPASS 1526#define IMXRT1050_CLK_PLL2_BYPASS 1627#define IMXRT1050_CLK_PLL3_BYPASS 1728#define IMXRT1050_CLK_PLL5_BYPASS 1929#define IMXRT1050_CLK_PLL1_REF_SEL 2030#define IMXRT1050_CLK_PLL2_REF_SEL 2131#define IMXRT1050_CLK_PLL3_REF_SEL 2232#define IMXRT1050_CLK_PLL5_REF_SEL 2333#define IMXRT1050_CLK_PRE_PERIPH_SEL 2434#define IMXRT1050_CLK_PERIPH_SEL 2535#define IMXRT1050_CLK_SEMC_ALT_SEL 2636#define IMXRT1050_CLK_SEMC_SEL 2737#define IMXRT1050_CLK_USDHC1_SEL 2838#define IMXRT1050_CLK_USDHC2_SEL 2939#define IMXRT1050_CLK_LPUART_SEL 3040#define IMXRT1050_CLK_LCDIF_SEL 3141#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 3242#define IMXRT1050_CLK_VIDEO_DIV 3343#define IMXRT1050_CLK_ARM_PODF 3444#define IMXRT1050_CLK_LPUART_PODF 3545#define IMXRT1050_CLK_USDHC1_PODF 3646#define IMXRT1050_CLK_USDHC2_PODF 3747#define IMXRT1050_CLK_SEMC_PODF 3848#define IMXRT1050_CLK_AHB_PODF 3949#define IMXRT1050_CLK_LCDIF_PRED 4050#define IMXRT1050_CLK_LCDIF_PODF 4151#define IMXRT1050_CLK_USDHC1 4252#define IMXRT1050_CLK_USDHC2 4353#define IMXRT1050_CLK_LPUART1 4454#define IMXRT1050_CLK_SEMC 4555#define IMXRT1050_CLK_LCDIF_APB 4656#define IMXRT1050_CLK_PLL1_ARM 4757#define IMXRT1050_CLK_PLL2_SYS 4858#define IMXRT1050_CLK_PLL3_USB_OTG 4959#define IMXRT1050_CLK_PLL4_AUDIO 5060#define IMXRT1050_CLK_PLL5_VIDEO 5161#define IMXRT1050_CLK_PLL6_ENET 5262#define IMXRT1050_CLK_PLL7_USB_HOST 5363#define IMXRT1050_CLK_LCDIF_PIX 5464#define IMXRT1050_CLK_USBOH3 5565#define IMXRT1050_CLK_IPG_PDOF 5666#define IMXRT1050_CLK_PER_CLK_SEL 5767#define IMXRT1050_CLK_PER_PDOF 5868#define IMXRT1050_CLK_DMA 5969#define IMXRT1050_CLK_DMA_MUX 6070#define IMXRT1050_CLK_END 6171 72#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */73