40 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides clock numbers for the ingenic,jz4740-cgu DT binding.4 *5 * They are roughly ordered as:6 * - external clocks7 * - PLLs8 * - muxes/dividers in the order they appear in the jz4740 programmers manual9 * - gates in order of their bit in the CLKGR* registers10 */11 12#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__13#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__14 15#define JZ4740_CLK_EXT 016#define JZ4740_CLK_RTC 117#define JZ4740_CLK_PLL 218#define JZ4740_CLK_PLL_HALF 319#define JZ4740_CLK_CCLK 420#define JZ4740_CLK_HCLK 521#define JZ4740_CLK_PCLK 622#define JZ4740_CLK_MCLK 723#define JZ4740_CLK_LCD 824#define JZ4740_CLK_LCD_PCLK 925#define JZ4740_CLK_I2S 1026#define JZ4740_CLK_SPI 1127#define JZ4740_CLK_MMC 1228#define JZ4740_CLK_UHC 1329#define JZ4740_CLK_UDC 1430#define JZ4740_CLK_UART0 1531#define JZ4740_CLK_UART1 1632#define JZ4740_CLK_DMA 1733#define JZ4740_CLK_IPU 1834#define JZ4740_CLK_ADC 1935#define JZ4740_CLK_I2C 2036#define JZ4740_CLK_AIC 2137#define JZ4740_CLK_TCU 2238 39#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */40