57 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides clock numbers for the ingenic,jz4760-cgu DT binding.4 */5 6#ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__7#define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__8 9#define JZ4760_CLK_EXT 010#define JZ4760_CLK_OSC32K 111#define JZ4760_CLK_PLL0 212#define JZ4760_CLK_PLL0_HALF 313#define JZ4760_CLK_PLL1 414#define JZ4760_CLK_CCLK 515#define JZ4760_CLK_HCLK 616#define JZ4760_CLK_SCLK 717#define JZ4760_CLK_H2CLK 818#define JZ4760_CLK_MCLK 919#define JZ4760_CLK_PCLK 1020#define JZ4760_CLK_MMC_MUX 1121#define JZ4760_CLK_MMC0 1222#define JZ4760_CLK_MMC1 1323#define JZ4760_CLK_MMC2 1424#define JZ4760_CLK_CIM 1525#define JZ4760_CLK_UHC 1626#define JZ4760_CLK_GPU 1727#define JZ4760_CLK_GPS 1828#define JZ4760_CLK_SSI_MUX 1929#define JZ4760_CLK_PCM 2030#define JZ4760_CLK_I2S 2131#define JZ4760_CLK_OTG 2232#define JZ4760_CLK_SSI0 2333#define JZ4760_CLK_SSI1 2434#define JZ4760_CLK_SSI2 2535#define JZ4760_CLK_DMA 2636#define JZ4760_CLK_I2C0 2737#define JZ4760_CLK_I2C1 2838#define JZ4760_CLK_UART0 2939#define JZ4760_CLK_UART1 3040#define JZ4760_CLK_UART2 3141#define JZ4760_CLK_UART3 3242#define JZ4760_CLK_IPU 3343#define JZ4760_CLK_ADC 3444#define JZ4760_CLK_AIC 3545#define JZ4760_CLK_VPU 3646#define JZ4760_CLK_UHC_PHY 3747#define JZ4760_CLK_OTG_PHY 3848#define JZ4760_CLK_EXT512 3949#define JZ4760_CLK_RTC 4050#define JZ4760_CLK_LPCLK_DIV 4151#define JZ4760_CLK_TVE 4252#define JZ4760_CLK_LPCLK 4353#define JZ4760_CLK_MDMA 4454#define JZ4760_CLK_BDMA 4555 56#endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */57