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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.4 *5 * They are roughly ordered as:6 * - external clocks7 * - PLLs8 * - muxes/dividers in the order they appear in the jz4780 programmers manual9 * - gates in order of their bit in the CLKGR* registers10 */11 12#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__13#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__14 15#define JZ4780_CLK_EXCLK 016#define JZ4780_CLK_RTCLK 117#define JZ4780_CLK_APLL 218#define JZ4780_CLK_MPLL 319#define JZ4780_CLK_EPLL 420#define JZ4780_CLK_VPLL 521#define JZ4780_CLK_OTGPHY 622#define JZ4780_CLK_SCLKA 723#define JZ4780_CLK_CPUMUX 824#define JZ4780_CLK_CPU 925#define JZ4780_CLK_L2CACHE 1026#define JZ4780_CLK_AHB0 1127#define JZ4780_CLK_AHB2PMUX 1228#define JZ4780_CLK_AHB2 1329#define JZ4780_CLK_PCLK 1430#define JZ4780_CLK_DDR 1531#define JZ4780_CLK_VPU 1632#define JZ4780_CLK_I2SPLL 1733#define JZ4780_CLK_I2S 1834#define JZ4780_CLK_LCD0PIXCLK 1935#define JZ4780_CLK_LCD1PIXCLK 2036#define JZ4780_CLK_MSCMUX 2137#define JZ4780_CLK_MSC0 2238#define JZ4780_CLK_MSC1 2339#define JZ4780_CLK_MSC2 2440#define JZ4780_CLK_UHC 2541#define JZ4780_CLK_SSIPLL 2642#define JZ4780_CLK_SSI 2743#define JZ4780_CLK_CIMMCLK 2844#define JZ4780_CLK_PCMPLL 2945#define JZ4780_CLK_PCM 3046#define JZ4780_CLK_GPU 3147#define JZ4780_CLK_HDMI 3248#define JZ4780_CLK_BCH 3349#define JZ4780_CLK_NEMC 3450#define JZ4780_CLK_OTG0 3551#define JZ4780_CLK_SSI0 3652#define JZ4780_CLK_SMB0 3753#define JZ4780_CLK_SMB1 3854#define JZ4780_CLK_SCC 3955#define JZ4780_CLK_AIC 4056#define JZ4780_CLK_TSSI0 4157#define JZ4780_CLK_OWI 4258#define JZ4780_CLK_KBC 4359#define JZ4780_CLK_SADC 4460#define JZ4780_CLK_UART0 4561#define JZ4780_CLK_UART1 4662#define JZ4780_CLK_UART2 4763#define JZ4780_CLK_UART3 4864#define JZ4780_CLK_SSI1 4965#define JZ4780_CLK_SSI2 5066#define JZ4780_CLK_PDMA 5167#define JZ4780_CLK_GPS 5268#define JZ4780_CLK_MAC 5369#define JZ4780_CLK_SMB2 5470#define JZ4780_CLK_CIM 5571#define JZ4780_CLK_LCD 5672#define JZ4780_CLK_TVE 5773#define JZ4780_CLK_IPU 5874#define JZ4780_CLK_DDR0 5975#define JZ4780_CLK_DDR1 6076#define JZ4780_CLK_SMB3 6177#define JZ4780_CLK_TSSI1 6278#define JZ4780_CLK_COMPRESS 6379#define JZ4780_CLK_AIC1 6480#define JZ4780_CLK_GPVLC 6581#define JZ4780_CLK_OTG1 6682#define JZ4780_CLK_UART4 6783#define JZ4780_CLK_AHBMON 6884#define JZ4780_CLK_SMB4 6985#define JZ4780_CLK_DES 7086#define JZ4780_CLK_X2D 7187#define JZ4780_CLK_CORE1 7288#define JZ4780_CLK_EXCLK_DIV512 7389#define JZ4780_CLK_RTC 7490 91#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */92