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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides clock numbers for the ingenic,x1000-cgu DT binding.4 *5 * They are roughly ordered as:6 * - external clocks7 * - PLLs8 * - muxes/dividers in the order they appear in the x1000 programmers manual9 * - gates in order of their bit in the CLKGR* registers10 */11 12#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__13#define __DT_BINDINGS_CLOCK_X1000_CGU_H__14 15#define X1000_CLK_EXCLK 016#define X1000_CLK_RTCLK 117#define X1000_CLK_APLL 218#define X1000_CLK_MPLL 319#define X1000_CLK_OTGPHY 420#define X1000_CLK_SCLKA 521#define X1000_CLK_CPUMUX 622#define X1000_CLK_CPU 723#define X1000_CLK_L2CACHE 824#define X1000_CLK_AHB0 925#define X1000_CLK_AHB2PMUX 1026#define X1000_CLK_AHB2 1127#define X1000_CLK_PCLK 1228#define X1000_CLK_DDR 1329#define X1000_CLK_MAC 1430#define X1000_CLK_LCD 1531#define X1000_CLK_MSCMUX 1632#define X1000_CLK_MSC0 1733#define X1000_CLK_MSC1 1834#define X1000_CLK_OTG 1935#define X1000_CLK_SSIPLL 2036#define X1000_CLK_SSIPLL_DIV2 2137#define X1000_CLK_SSIMUX 2238#define X1000_CLK_EMC 2339#define X1000_CLK_EFUSE 2440#define X1000_CLK_SFC 2541#define X1000_CLK_I2C0 2642#define X1000_CLK_I2C1 2743#define X1000_CLK_I2C2 2844#define X1000_CLK_UART0 2945#define X1000_CLK_UART1 3046#define X1000_CLK_UART2 3147#define X1000_CLK_TCU 3248#define X1000_CLK_SSI 3349#define X1000_CLK_OST 3450#define X1000_CLK_PDMA 3551#define X1000_CLK_EXCLK_DIV512 3652#define X1000_CLK_RTC 3753#define X1000_CLK_AIC 3854#define X1000_CLK_I2SPLLMUX 3955#define X1000_CLK_I2SPLL 4056#define X1000_CLK_I2S 4157 58#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */59