58 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides clock numbers for the ingenic,x1830-cgu DT binding.4 *5 * They are roughly ordered as:6 * - external clocks7 * - PLLs8 * - muxes/dividers in the order they appear in the x1830 programmers manual9 * - gates in order of their bit in the CLKGR* registers10 */11 12#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__13#define __DT_BINDINGS_CLOCK_X1830_CGU_H__14 15#define X1830_CLK_EXCLK 016#define X1830_CLK_RTCLK 117#define X1830_CLK_APLL 218#define X1830_CLK_MPLL 319#define X1830_CLK_EPLL 420#define X1830_CLK_VPLL 521#define X1830_CLK_OTGPHY 622#define X1830_CLK_SCLKA 723#define X1830_CLK_CPUMUX 824#define X1830_CLK_CPU 925#define X1830_CLK_L2CACHE 1026#define X1830_CLK_AHB0 1127#define X1830_CLK_AHB2PMUX 1228#define X1830_CLK_AHB2 1329#define X1830_CLK_PCLK 1430#define X1830_CLK_DDR 1531#define X1830_CLK_MAC 1632#define X1830_CLK_LCD 1733#define X1830_CLK_MSCMUX 1834#define X1830_CLK_MSC0 1935#define X1830_CLK_MSC1 2036#define X1830_CLK_SSIPLL 2137#define X1830_CLK_SSIPLL_DIV2 2238#define X1830_CLK_SSIMUX 2339#define X1830_CLK_EMC 2440#define X1830_CLK_EFUSE 2541#define X1830_CLK_OTG 2642#define X1830_CLK_SSI0 2743#define X1830_CLK_SMB0 2844#define X1830_CLK_SMB1 2945#define X1830_CLK_SMB2 3046#define X1830_CLK_UART0 3147#define X1830_CLK_UART1 3248#define X1830_CLK_SSI1 3349#define X1830_CLK_SFC 3450#define X1830_CLK_PDMA 3551#define X1830_CLK_TCU 3652#define X1830_CLK_DTRNG 3753#define X1830_CLK_OST 3854#define X1830_CLK_EXCLK_DIV512 3955#define X1830_CLK_RTC 4056 57#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */58