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1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */2/*3 * Copyright (C) 2023, Intel Corporation4 */5 6#ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H7#define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H8 9/* fixed rate clocks */10#define AGILEX5_OSC1 011#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 112#define AGILEX5_CB_INTOSC_LS_CLK 213#define AGILEX5_F2S_FREE_CLK 314 15/* PLL clocks */16#define AGILEX5_MAIN_PLL_CLK 417#define AGILEX5_MAIN_PLL_C0_CLK 518#define AGILEX5_MAIN_PLL_C1_CLK 619#define AGILEX5_MAIN_PLL_C2_CLK 720#define AGILEX5_MAIN_PLL_C3_CLK 821#define AGILEX5_PERIPH_PLL_CLK 922#define AGILEX5_PERIPH_PLL_C0_CLK 1023#define AGILEX5_PERIPH_PLL_C1_CLK 1124#define AGILEX5_PERIPH_PLL_C2_CLK 1225#define AGILEX5_PERIPH_PLL_C3_CLK 1326#define AGILEX5_CORE0_FREE_CLK 1427#define AGILEX5_CORE1_FREE_CLK 1528#define AGILEX5_CORE2_FREE_CLK 1629#define AGILEX5_CORE3_FREE_CLK 1730#define AGILEX5_DSU_FREE_CLK 1831#define AGILEX5_BOOT_CLK 1932 33/* fixed factor clocks */34#define AGILEX5_L3_MAIN_FREE_CLK 2035#define AGILEX5_NOC_FREE_CLK 2136#define AGILEX5_S2F_USR0_CLK 2237#define AGILEX5_NOC_CLK 2338#define AGILEX5_EMAC_A_FREE_CLK 2439#define AGILEX5_EMAC_B_FREE_CLK 2540#define AGILEX5_EMAC_PTP_FREE_CLK 2641#define AGILEX5_GPIO_DB_FREE_CLK 2742#define AGILEX5_S2F_USER0_FREE_CLK 2843#define AGILEX5_S2F_USER1_FREE_CLK 2944#define AGILEX5_PSI_REF_FREE_CLK 3045#define AGILEX5_USB31_FREE_CLK 3146 47/* Gate clocks */48#define AGILEX5_CORE0_CLK 3249#define AGILEX5_CORE1_CLK 3350#define AGILEX5_CORE2_CLK 3451#define AGILEX5_CORE3_CLK 3552#define AGILEX5_MPU_CLK 3653#define AGILEX5_MPU_PERIPH_CLK 3754#define AGILEX5_MPU_CCU_CLK 3855#define AGILEX5_L4_MAIN_CLK 3956#define AGILEX5_L4_MP_CLK 4057#define AGILEX5_L4_SYS_FREE_CLK 4158#define AGILEX5_L4_SP_CLK 4259#define AGILEX5_CS_AT_CLK 4360#define AGILEX5_CS_TRACE_CLK 4461#define AGILEX5_CS_PDBG_CLK 4562#define AGILEX5_EMAC1_CLK 4763#define AGILEX5_EMAC2_CLK 4864#define AGILEX5_EMAC_PTP_CLK 4965#define AGILEX5_GPIO_DB_CLK 5066#define AGILEX5_S2F_USER0_CLK 5167#define AGILEX5_S2F_USER1_CLK 5268#define AGILEX5_PSI_REF_CLK 5369#define AGILEX5_USB31_SUSPEND_CLK 5470#define AGILEX5_EMAC0_CLK 4671#define AGILEX5_USB31_BUS_CLK_EARLY 5572#define AGILEX5_USB2OTG_HCLK 5673#define AGILEX5_SPIM_0_CLK 5774#define AGILEX5_SPIM_1_CLK 5875#define AGILEX5_SPIS_0_CLK 5976#define AGILEX5_SPIS_1_CLK 6077#define AGILEX5_DMA_CORE_CLK 6178#define AGILEX5_DMA_HS_CLK 6279#define AGILEX5_I3C_0_CORE_CLK 6380#define AGILEX5_I3C_1_CORE_CLK 6481#define AGILEX5_I2C_0_PCLK 6582#define AGILEX5_I2C_1_PCLK 6683#define AGILEX5_I2C_EMAC0_PCLK 6784#define AGILEX5_I2C_EMAC1_PCLK 6885#define AGILEX5_I2C_EMAC2_PCLK 6986#define AGILEX5_UART_0_PCLK 7087#define AGILEX5_UART_1_PCLK 7188#define AGILEX5_SPTIMER_0_PCLK 7289#define AGILEX5_SPTIMER_1_PCLK 7390#define AGILEX5_DFI_CLK 7491#define AGILEX5_NAND_NF_CLK 7592#define AGILEX5_NAND_BCH_CLK 7693#define AGILEX5_SDMMC_SDPHY_REG_CLK 7794#define AGILEX5_SDMCLK 7895#define AGILEX5_SOFTPHY_REG_PCLK 7996#define AGILEX5_SOFTPHY_PHY_CLK 8097#define AGILEX5_SOFTPHY_CTRL_CLK 8198#define AGILEX5_NUM_CLKS 8299 100#endif /* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */101