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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (C) 2020 Intel Corporation.4 * Lei Chuanhua <Chuanhua.lei@intel.com>5 * Zhu Yixin <Yixin.zhu@intel.com>6 */7#ifndef __INTEL_LGM_CLK_H8#define __INTEL_LGM_CLK_H9 10/* PLL clocks */11#define LGM_CLK_OSC 112#define LGM_CLK_PLLPP 213#define LGM_CLK_PLL2 314#define LGM_CLK_PLL0CZ 415#define LGM_CLK_PLL0B 516#define LGM_CLK_PLL1 617#define LGM_CLK_LJPLL3 718#define LGM_CLK_LJPLL4 819#define LGM_CLK_PLL0CM0 920#define LGM_CLK_PLL0CM1 1021 22/* clocks from PLLs */23 24/* ROPLL clocks */25#define LGM_CLK_PP_HW 1526#define LGM_CLK_PP_UC 1627#define LGM_CLK_PP_FXD 1728#define LGM_CLK_PP_TBM 1829 30/* PLL2 clocks */31#define LGM_CLK_DDR 2032 33/* PLL0CZ */34#define LGM_CLK_CM 2535#define LGM_CLK_IC 2636#define LGM_CLK_SDXC3 2737 38/* PLL0B */39#define LGM_CLK_NGI 3040#define LGM_CLK_NOC4 3141#define LGM_CLK_SW 3242#define LGM_CLK_QSPI 3343#define LGM_CLK_CQEM LGM_CLK_SW44#define LGM_CLK_EMMC5 LGM_CLK_NOC445 46/* PLL1 */47#define LGM_CLK_CT 3548#define LGM_CLK_DSP 3649#define LGM_CLK_VIF 3750 51/* LJPLL3 */52#define LGM_CLK_CML 4053#define LGM_CLK_SERDES 4154#define LGM_CLK_POOL 4255#define LGM_CLK_PTP 4356 57/* LJPLL4 */58#define LGM_CLK_PCIE 4559#define LGM_CLK_SATA LGM_CLK_PCIE60 61/* PLL0CM0 */62#define LGM_CLK_CPU0 5063 64/* PLL0CM1 */65#define LGM_CLK_CPU1 5566 67/* Miscellaneous clocks */68#define LGM_CLK_EMMC4 6069#define LGM_CLK_SDXC2 6170#define LGM_CLK_EMMC 6271#define LGM_CLK_SDXC 6372#define LGM_CLK_SLIC 6473#define LGM_CLK_DCL 6574#define LGM_CLK_DOCSIS 6675#define LGM_CLK_PCM 6776#define LGM_CLK_DDR_PHY 6877#define LGM_CLK_PONDEF 6978#define LGM_CLK_PL25M 7079#define LGM_CLK_PL10M 7180#define LGM_CLK_PL1544K 7281#define LGM_CLK_PL2048K 7382#define LGM_CLK_PL8K 7483#define LGM_CLK_PON_NTR 7584#define LGM_CLK_SYNC0 7685#define LGM_CLK_SYNC1 7786#define LGM_CLK_PROGDIV 7887#define LGM_CLK_OD0 7988#define LGM_CLK_OD1 8089#define LGM_CLK_CBPHY0 8190#define LGM_CLK_CBPHY1 8291#define LGM_CLK_CBPHY2 8392#define LGM_CLK_CBPHY3 8493 94/* Gate clocks */95/* Gate CLK0 */96#define LGM_GCLK_C55 10097#define LGM_GCLK_QSPI 10198#define LGM_GCLK_EIP197 10299#define LGM_GCLK_VAULT 103100#define LGM_GCLK_TOE 104101#define LGM_GCLK_SDXC 105102#define LGM_GCLK_EMMC 106103#define LGM_GCLK_SPI_DBG 107104#define LGM_GCLK_DMA3 108105 106/* Gate CLK1 */107#define LGM_GCLK_DMA0 120108#define LGM_GCLK_LEDC0 121109#define LGM_GCLK_LEDC1 122110#define LGM_GCLK_I2S0 123111#define LGM_GCLK_I2S1 124112#define LGM_GCLK_EBU 125113#define LGM_GCLK_PWM 126114#define LGM_GCLK_I2C0 127115#define LGM_GCLK_I2C1 128116#define LGM_GCLK_I2C2 129117#define LGM_GCLK_I2C3 130118#define LGM_GCLK_SSC0 131119#define LGM_GCLK_SSC1 132120#define LGM_GCLK_SSC2 133121#define LGM_GCLK_SSC3 134122#define LGM_GCLK_GPTC0 135123#define LGM_GCLK_GPTC1 136124#define LGM_GCLK_GPTC2 137125#define LGM_GCLK_GPTC3 138126#define LGM_GCLK_ASC0 139127#define LGM_GCLK_ASC1 140128#define LGM_GCLK_ASC2 141129#define LGM_GCLK_ASC3 142130#define LGM_GCLK_PCM0 143131#define LGM_GCLK_PCM1 144132#define LGM_GCLK_PCM2 145133 134/* Gate CLK2 */135#define LGM_GCLK_PCIE10 150136#define LGM_GCLK_PCIE11 151137#define LGM_GCLK_PCIE30 152138#define LGM_GCLK_PCIE31 153139#define LGM_GCLK_PCIE20 154140#define LGM_GCLK_PCIE21 155141#define LGM_GCLK_PCIE40 156142#define LGM_GCLK_PCIE41 157143#define LGM_GCLK_XPCS0 158144#define LGM_GCLK_XPCS1 159145#define LGM_GCLK_XPCS2 160146#define LGM_GCLK_XPCS3 161147#define LGM_GCLK_SATA0 162148#define LGM_GCLK_SATA1 163149#define LGM_GCLK_SATA2 164150#define LGM_GCLK_SATA3 165151 152/* Gate CLK3 */153#define LGM_GCLK_ARCEM4 170154#define LGM_GCLK_IDMAR1 171155#define LGM_GCLK_IDMAT0 172156#define LGM_GCLK_IDMAT1 173157#define LGM_GCLK_IDMAT2 174158#define LGM_GCLK_PPV4 175159#define LGM_GCLK_GSWIPO 176160#define LGM_GCLK_CQEM 177161#define LGM_GCLK_XPCS5 178162#define LGM_GCLK_USB1 179163#define LGM_GCLK_USB2 180164 165#endif /* __INTEL_LGM_CLK_H */166