54 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>4 * Copyright (c) 2020 Western Digital Corporation or its affiliates.5 */6#ifndef CLOCK_K210_CLK_H7#define CLOCK_K210_CLK_H8 9/*10 * Kendryte K210 SoC clock identifiers (arbitrary values).11 */12#define K210_CLK_CPU 013#define K210_CLK_SRAM0 114#define K210_CLK_SRAM1 215#define K210_CLK_AI 316#define K210_CLK_DMA 417#define K210_CLK_FFT 518#define K210_CLK_ROM 619#define K210_CLK_DVP 720#define K210_CLK_APB0 821#define K210_CLK_APB1 922#define K210_CLK_APB2 1023#define K210_CLK_I2S0 1124#define K210_CLK_I2S1 1225#define K210_CLK_I2S2 1326#define K210_CLK_I2S0_M 1427#define K210_CLK_I2S1_M 1528#define K210_CLK_I2S2_M 1629#define K210_CLK_WDT0 1730#define K210_CLK_WDT1 1831#define K210_CLK_SPI0 1932#define K210_CLK_SPI1 2033#define K210_CLK_SPI2 2134#define K210_CLK_I2C0 2235#define K210_CLK_I2C1 2336#define K210_CLK_I2C2 2437#define K210_CLK_SPI3 2538#define K210_CLK_TIMER0 2639#define K210_CLK_TIMER1 2740#define K210_CLK_TIMER2 2841#define K210_CLK_GPIO 2942#define K210_CLK_UART1 3043#define K210_CLK_UART2 3144#define K210_CLK_UART3 3245#define K210_CLK_FPIOA 3346#define K210_CLK_SHA 3447#define K210_CLK_AES 3548#define K210_CLK_OTP 3649#define K210_CLK_RTC 3750 51#define K210_NUM_CLKS 3852 53#endif /* CLOCK_K210_CLK_H */54