75 lines · c
1/*2 * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>3 *4 * This code is released using a dual license strategy: BSD/GPL5 * You can choose the licence that better fits your requirements.6 *7 * Released under the terms of 3-clause BSD License8 * Released under the terms of GNU General Public License Version 2.09 *10 */11 12/* Clock Control Unit 1 (CCU1) clock offsets */13#define CLK_APB3_BUS 0x10014#define CLK_APB3_I2C1 0x10815#define CLK_APB3_DAC 0x11016#define CLK_APB3_ADC0 0x11817#define CLK_APB3_ADC1 0x12018#define CLK_APB3_CAN0 0x12819#define CLK_APB1_BUS 0x20020#define CLK_APB1_MOTOCON_PWM 0x20821#define CLK_APB1_I2C0 0x21022#define CLK_APB1_I2S 0x21823#define CLK_APB1_CAN1 0x22024#define CLK_SPIFI 0x30025#define CLK_CPU_BUS 0x40026#define CLK_CPU_SPIFI 0x40827#define CLK_CPU_GPIO 0x41028#define CLK_CPU_LCD 0x41829#define CLK_CPU_ETHERNET 0x42030#define CLK_CPU_USB0 0x42831#define CLK_CPU_EMC 0x43032#define CLK_CPU_SDIO 0x43833#define CLK_CPU_DMA 0x44034#define CLK_CPU_CORE 0x44835#define CLK_CPU_SCT 0x46836#define CLK_CPU_USB1 0x47037#define CLK_CPU_EMCDIV 0x47838#define CLK_CPU_FLASHA 0x48039#define CLK_CPU_FLASHB 0x48840#define CLK_CPU_M0APP 0x49041#define CLK_CPU_ADCHS 0x49842#define CLK_CPU_EEPROM 0x4a043#define CLK_CPU_WWDT 0x50044#define CLK_CPU_UART0 0x50845#define CLK_CPU_UART1 0x51046#define CLK_CPU_SSP0 0x51847#define CLK_CPU_TIMER0 0x52048#define CLK_CPU_TIMER1 0x52849#define CLK_CPU_SCU 0x53050#define CLK_CPU_CREG 0x53851#define CLK_CPU_RITIMER 0x60052#define CLK_CPU_UART2 0x60853#define CLK_CPU_UART3 0x61054#define CLK_CPU_TIMER2 0x61855#define CLK_CPU_TIMER3 0x62056#define CLK_CPU_SSP1 0x62857#define CLK_CPU_QEI 0x63058#define CLK_PERIPH_BUS 0x70059#define CLK_PERIPH_CORE 0x71060#define CLK_PERIPH_SGPIO 0x71861#define CLK_USB0 0x80062#define CLK_USB1 0x90063#define CLK_SPI 0xA0064#define CLK_ADCHS 0xB0065 66/* Clock Control Unit 2 (CCU2) clock offsets */67#define CLK_AUDIO 0x10068#define CLK_APB2_UART3 0x20069#define CLK_APB2_UART2 0x30070#define CLK_APB0_UART1 0x40071#define CLK_APB0_UART0 0x50072#define CLK_APB2_SSP1 0x60073#define CLK_APB0_SSP0 0x70074#define CLK_SDIO 0x80075