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1/*2 * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>3 *4 * This code is released using a dual license strategy: BSD/GPL5 * You can choose the licence that better fits your requirements.6 *7 * Released under the terms of 3-clause BSD License8 * Released under the terms of GNU General Public License Version 2.09 *10 */11 12/* LPC18xx/43xx base clock ids */13#define BASE_SAFE_CLK 014#define BASE_USB0_CLK 115#define BASE_PERIPH_CLK 216#define BASE_USB1_CLK 317#define BASE_CPU_CLK 418#define BASE_SPIFI_CLK 519#define BASE_SPI_CLK 620#define BASE_PHY_RX_CLK 721#define BASE_PHY_TX_CLK 822#define BASE_APB1_CLK 923#define BASE_APB3_CLK 1024#define BASE_LCD_CLK 1125#define BASE_ADCHS_CLK 1226#define BASE_SDIO_CLK 1327#define BASE_SSP0_CLK 1428#define BASE_SSP1_CLK 1529#define BASE_UART0_CLK 1630#define BASE_UART1_CLK 1731#define BASE_UART2_CLK 1832#define BASE_UART3_CLK 1933#define BASE_OUT_CLK 2034#define BASE_RES1_CLK 2135#define BASE_RES2_CLK 2236#define BASE_RES3_CLK 2337#define BASE_RES4_CLK 2438#define BASE_AUDIO_CLK 2539#define BASE_CGU_OUT0_CLK 2640#define BASE_CGU_OUT1_CLK 2741#define BASE_CLK_MAX (BASE_CGU_OUT1_CLK + 1)42