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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __DTS_MARVELL_MMP2_CLOCK_H3#define __DTS_MARVELL_MMP2_CLOCK_H4 5/* fixed clocks and plls */6#define MMP2_CLK_CLK32 17#define MMP2_CLK_VCTCXO 28#define MMP2_CLK_PLL1 39#define MMP2_CLK_PLL1_2 810#define MMP2_CLK_PLL1_4 911#define MMP2_CLK_PLL1_8 1012#define MMP2_CLK_PLL1_16 1113#define MMP2_CLK_PLL1_3 1214#define MMP2_CLK_PLL1_6 1315#define MMP2_CLK_PLL1_12 1416#define MMP2_CLK_PLL1_20 1517#define MMP2_CLK_PLL2 1618#define MMP2_CLK_PLL2_2 1719#define MMP2_CLK_PLL2_4 1820#define MMP2_CLK_PLL2_8 1921#define MMP2_CLK_PLL2_16 2022#define MMP2_CLK_PLL2_3 2123#define MMP2_CLK_PLL2_6 2224#define MMP2_CLK_PLL2_12 2325#define MMP2_CLK_VCTCXO_2 2426#define MMP2_CLK_VCTCXO_4 2527#define MMP2_CLK_UART_PLL 2628#define MMP2_CLK_USB_PLL 2729#define MMP3_CLK_PLL1_P 2830#define MMP3_CLK_PLL2_P 2931#define MMP3_CLK_PLL3 3032#define MMP2_CLK_I2S0 3133#define MMP2_CLK_I2S1 3234 35/* apb peripherals */36#define MMP2_CLK_TWSI0 6037#define MMP2_CLK_TWSI1 6138#define MMP2_CLK_TWSI2 6239#define MMP2_CLK_TWSI3 6340#define MMP2_CLK_TWSI4 6441#define MMP2_CLK_TWSI5 6542#define MMP2_CLK_GPIO 6643#define MMP2_CLK_KPC 6744#define MMP2_CLK_RTC 6845#define MMP2_CLK_PWM0 6946#define MMP2_CLK_PWM1 7047#define MMP2_CLK_PWM2 7148#define MMP2_CLK_PWM3 7249#define MMP2_CLK_UART0 7350#define MMP2_CLK_UART1 7451#define MMP2_CLK_UART2 7552#define MMP2_CLK_UART3 7653#define MMP2_CLK_SSP0 7754#define MMP2_CLK_SSP1 7855#define MMP2_CLK_SSP2 7956#define MMP2_CLK_SSP3 8057#define MMP2_CLK_TIMER 8158#define MMP2_CLK_THERMAL0 8259#define MMP3_CLK_THERMAL1 8360#define MMP3_CLK_THERMAL2 8461#define MMP3_CLK_THERMAL3 8562 63/* axi peripherals */64#define MMP2_CLK_SDH0 10165#define MMP2_CLK_SDH1 10266#define MMP2_CLK_SDH2 10367#define MMP2_CLK_SDH3 10468#define MMP2_CLK_USB 10569#define MMP2_CLK_DISP0 10670#define MMP2_CLK_DISP0_MUX 10771#define MMP2_CLK_DISP0_SPHY 10872#define MMP2_CLK_DISP1 10973#define MMP2_CLK_DISP1_MUX 11074#define MMP2_CLK_CCIC_ARBITER 11175#define MMP2_CLK_CCIC0 11276#define MMP2_CLK_CCIC0_MIX 11377#define MMP2_CLK_CCIC0_PHY 11478#define MMP2_CLK_CCIC0_SPHY 11579#define MMP2_CLK_CCIC1 11680#define MMP2_CLK_CCIC1_MIX 11781#define MMP2_CLK_CCIC1_PHY 11882#define MMP2_CLK_CCIC1_SPHY 11983#define MMP2_CLK_DISP0_LCDC 12084#define MMP2_CLK_USBHSIC0 12185#define MMP2_CLK_USBHSIC1 12286#define MMP2_CLK_GPU_BUS 12387#define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS88#define MMP2_CLK_GPU_3D 12489#define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D90#define MMP3_CLK_GPU_2D 12591#define MMP3_CLK_SDH4 12692#define MMP2_CLK_AUDIO 12793 94#endif95