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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __DTS_MARVELL_PXA168_CLOCK_H3#define __DTS_MARVELL_PXA168_CLOCK_H4 5/* fixed clocks and plls */6#define PXA168_CLK_CLK32 17#define PXA168_CLK_VCTCXO 28#define PXA168_CLK_PLL1 39#define PXA168_CLK_PLL1_2 810#define PXA168_CLK_PLL1_4 911#define PXA168_CLK_PLL1_8 1012#define PXA168_CLK_PLL1_16 1113#define PXA168_CLK_PLL1_6 1214#define PXA168_CLK_PLL1_12 1315#define PXA168_CLK_PLL1_24 1416#define PXA168_CLK_PLL1_48 1517#define PXA168_CLK_PLL1_96 1618#define PXA168_CLK_PLL1_13 1719#define PXA168_CLK_PLL1_13_1_5 1820#define PXA168_CLK_PLL1_2_1_5 1921#define PXA168_CLK_PLL1_3_16 2022#define PXA168_CLK_PLL1_192 2123#define PXA168_CLK_PLL1_2_1_10 2224#define PXA168_CLK_PLL1_2_3_16 2325#define PXA168_CLK_UART_PLL 2726#define PXA168_CLK_USB_PLL 2827#define PXA168_CLK_CLK32_2 5028 29/* apb peripherals */30#define PXA168_CLK_TWSI0 6031#define PXA168_CLK_TWSI1 6132#define PXA168_CLK_TWSI2 6233#define PXA168_CLK_TWSI3 6334#define PXA168_CLK_GPIO 6435#define PXA168_CLK_KPC 6536#define PXA168_CLK_RTC 6637#define PXA168_CLK_PWM0 6738#define PXA168_CLK_PWM1 6839#define PXA168_CLK_PWM2 6940#define PXA168_CLK_PWM3 7041#define PXA168_CLK_UART0 7142#define PXA168_CLK_UART1 7243#define PXA168_CLK_UART2 7344#define PXA168_CLK_SSP0 7445#define PXA168_CLK_SSP1 7546#define PXA168_CLK_SSP2 7647#define PXA168_CLK_SSP3 7748#define PXA168_CLK_SSP4 7849#define PXA168_CLK_TIMER 7950 51/* axi peripherals */52#define PXA168_CLK_DFC 10053#define PXA168_CLK_SDH0 10154#define PXA168_CLK_SDH1 10255#define PXA168_CLK_SDH2 10356#define PXA168_CLK_USB 10457#define PXA168_CLK_SPH 10558#define PXA168_CLK_DISP0 10659#define PXA168_CLK_CCIC0 10760#define PXA168_CLK_CCIC0_PHY 10861#define PXA168_CLK_CCIC0_SPHY 10962#define PXA168_CLK_SDH3 11063#define PXA168_CLK_SDH01_AXI 11164#define PXA168_CLK_SDH23_AXI 11265 66#endif67